CAT28C257_04 Datasheet, PDF (5/12 Pages) Catalyst Semiconductor – 256K-Bit CMOS PARALLEL EEPROM

CAT28C257
A.C. CHARACTERISTICS, Write Cycle
VCC=5V±10%, unless otherwise specified
Symbol
t_WC
t_AS
t_AH
t_CS
t_CH
t_CW(3)
t_OES
t_OEH
t_WP(3)
t_DS
t_DH
t_INIT(1)
t_BLC(1)(4)
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
Data Setup Time
Data Hold Time
Write Inhibit Period After Power-up
Byte Load Cycle Time
28C257-12
Min Typ Max
5
0
50
0
0
100
0
0
100
50
0
0
5
10
0.1
100
28C257-15
Min Typ Max
5
0
50
0
0
100
0
0
100
50
5
10
0.1
100
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
Figure 1. A.C. Testing Input/Output Waveform(2)
VCC - 0.3V
0.0 V
INPUT PULSE LEVELS
2.0 V
0.8 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
DEVICE
UNDER
TEST
1.3V
1N914
3.3K
OUT
CL = 100 pF
Note:
CL INCLUDES JIG CAPACITANCE
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration t_BLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within t_BLC max. stops the timer.
5
Doc. No. 1015, Rev. D