CAT24FC16_05 Datasheet, PDF (5/11 Pages) Catalyst Semiconductor – 16-kb I2C Serial EEPROM

CAT24FC16
I²C BUS PROTOCOL
whether a Read or Write operation is to be performed.
The following defines the features of the I²C bus proto-
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
col:
After the Master sends a START condition and the slave
(1) Data transfer may be initiated only when the bus is _{address byte, the CAT24FC16 monitors the bus and}
not busy.
responds with an acknowledge (on the SDA line) when
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
its address matches the transmitted slave address. The
CAT24FC16 then performs a Read or a Write operation
depending on the state of the R/W bit.
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
t _{device, and is defined as a HIGH to LOW transition of}
r _{SDA when SCL is HIGH. The CAT24FC16 monitor the}
SDA and SCL lines and will not respond until this
a condition is met.
STOP Condition
P _{A LOW to HIGH transition of SDA when SCL is HIGH}
determines the STOP condition. All operations must end
with a STOP condition.
d _{DEVICE ADDRESSING}
e _{The Master begins a transmission by sending a START}
condition. The Master then sends the address of the
u _{particular slave device it is requesting. The four most}
significant bits of the 8-bit slave address are fixed as
tin ^{1010 for the CAT24FC16 (see Fig. 5). The next three}
significant bits (A10, A9, A8) are the memory array
address bits. The last bit of the slave address specifies
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24FC16 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
When the CAT24FC16 begins a READ mode, it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT24FC16 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
n _{Figure 4. Acknowledge Timing}
SCL FROM
1
o_MASTER
8
9
c_{DATA OUTPUT}
is^{FROM TRANSMITTER}
DATA OUTPUT
D ^{FROM RECEIVER}
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1 0 1 0 A10 A9 A8 R/W Normal Read and Write
DEVICE ADDRESS
5
Doc No. 1054, Rev. I