CAT5259_08 Datasheet, PDF (4/16 Pages) Catalyst Semiconductor – Quad Digitally Programmable Potentiometers (DPP™) with 256 Taps and I²C Interface

CAT5259
D.C. OPERATING CHARACTERISTICS
V_CC = +2.5V to +6.0V, unless otherwise specified.
Symbol Parameter
Test Conditions
Min
Max
I_CC1
I_CC2
I_SB
I_LI
I_LO
V_IL
V_IH
V_OL1
Power Supply Current
Power Supply Current
Non-volatile WRITE
Standby Current (V_CC = 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V_CC = 3.0V)
f_SCL = 400kHz, SDA = Open
V_CC = 6V, Inputs = GND
f_SCK = 400kHz, SDA Open
V_CC = 6V, Input = GND
V_IN = GND or V_CC, SDA = Open
V_IN = GND to V_CC
V_OUT = GND to V_CC
I_OL = 3 mA
-1
V_CC x 0.7
1
5
5
10
10
V_CC x 0.3
V_CC + 1.0
0.4
CAPACITANCE
T_A = 25ºC, f = 1.0MHz, V_CC = 5V
Symbol
C_I/O(1)
C_IN(1)
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL, ^{¯W¯P¯)}
Conditions
V_I/O = 0V
V_IN = 0V
Max.
8
6
A.C. CHARACTERISTICS
Symbol Parameter
2.5V - 6.0V
Min.
Max.
f_SCL
T_I(1)
t_AA
t_BUF(1)
t_HD:STA
t_LOW
t_HIGH
t_SU:STA
t_HD:DAT
t_SU:DAT
t_R(1)
t_F(1)
t_SU:STO
t_DH
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the bus must be free before a new transmission can start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition SetupTime (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
400
200
1
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
0.6
100
Units
mA
mA
µA
µA
µA
V
V
V
Units
pF
pF
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. MD-2000 Rev. H
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice