CAT25C11 Datasheet, PDF(4/12 Page) Catalyst Semiconductor – 1K/2K/4K/8K/16K SPI Serial CMOS EEPROM

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CAT25C11 Datasheet, PDF (4/12 Pages) Catalyst Semiconductor – 1K/2K/4K/8K/16K SPI Serial CMOS EEPROM

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CAT25C11/03/05/09/17

FUNCTIONAL DESCRIPTION

The CAT25C11/03/05/09/17 supports the SPI bus data

transmission protocol. The synchronous Serial Periph-

eral Interface (SPI) helps the CAT25C11/03/05/09/17 to

interface directly with many of todayâs popular

microcontrollers. The CAT25C11/03/05/09/17 contains

an 8-bit instruction register. (The instruction set and the

operation codes are detailed in the instruction set table)

After the device is selected with CS going low, the first

byte will be received. The part is accessed via the SI pin,

with data being clocked in on the rising edge of SCK.

The first byte contains one of the six op-codes that define

the operation to be performed.

PIN DESCRIPTION

SI: Serial Input

SI is the serial data input pin. This pin is used to input all

opcodes, byte addresses, and data to be written to the

25C11/03/05/09/17.Input data is latched on the rising

edge of the serial clock for SPI modes (0, 0 & 1, 1).

SO: Serial Output

SO is the serial data output pin. This pin is used to transfer

data out of the 25C11/03/05/09/17. During a read cycle,

data is shifted out on the falling edge of the serial clock for

Figure 1. Sychronous Data Timing

VIH

SCK

VIL

tCSS

VIH

VIL

VIH

VIL

tWH

tSU

VALID IN

VOH

VOL

HI-Z

Note: Dashed Line= mode (1, 1) â â â â

tCS

tCSH

tWL

tRI

tFI

tHO

tDIS

HI-Z

INSTRUCTION SET

Instruction

WREN

WRDI

RDSR

WRSR

READ

WRITE

Opcode

0000 0110

0000 0100

0000 0101

0000 0001

0000 X011(1)

0000 X010(1)

Operation

Enable Write Operations

Disable Write Operations

Read Status Register

Write Status Register

Read Data from Memory

Write Data to Memory

Power-Up Timing(2)(3)

Symbol

Parameter

Max.

tPUR

Power-up to Read Operation

tPUW

Power-up to Write Operation

Note:

(1) X=0 for 25C11, 25C03, 25C09, 25C17. X=A8 for 25C05

(2) This parameter is tested initially and after a design or process change that affects the parameter.

(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

Units

Doc. No. 1017, Rev. J

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