CAT522_0710 Datasheet, PDF (3/15 Pages) Catalyst Semiconductor – Configured Digitally Programmable Potentiometer (DPP™): Programmable Voltage Applications

ABSOLUTE MAXIMUM RATINGS ⁽¹⁾
Parameters
Ratings Units
Supply Voltage
V_DD to GND
Inputs
V
-0.5 to +7
CLK to GND
-0.5 to V_DD +0.5 V
CS to GND
-0.5 to V_DD +0.5 V
DI to GND
-0.5 to V_DD +0.5 V
RDY/¯B¯S¯Y¯ to GND -0.5 to V_DD +0.5 V
PROG to GND -0.5 to V_DD +0.5 V
V_REFH to GND
-0.5 to V_DD +0.5 V
V_REFL to GND
-0.5 to V_DD +0.5 V
CAT522
Parameters
Outputs
D₀ to GND
V_OUT 1– 4 to GND
Operating Ambient Temperature
Commercial
(‘C’ or Blank suffix)
Industrial (‘I’ suffix)
Junction Temperature
Storage Temperature
Lead Soldering (10s max)
Ratings
-0.5 to V_DD +0.5
-0.5 to V_DD +0.5
0 to +70
-40 to +85
+150
-65 to +150
+300
Units
V
V
°C
°C
°C
°C
°C
RELIABILITY CHARACTERISTICS
Symbol
V_ZAP(2)
I_LTH(2) ⁽³⁾
Parameter
ESD Susceptibility
Latch-Up
Test Method
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
2000
100
Max
Units
V
mA
POWER SUPPLY
Symbol Parameter
I_DD1
Supply Current (Read)
I_DD2
Supply Current (Write)
V_DD
Operating Voltage Range
Conditions
Normal Operating
Programming, V_DD = 5V
V_DD = 3V
Min Typ Max Units
— 400 600 µA
— 1600 2500 µA
— 1000 1600 µA
2.7 — 5.5
V
LOGIC INPUTS
Symbol Parameter
I_IH
Input Leakage Current
I_IL
Input Leakage Current
V_IH
High Level Input Voltage
V_IL
Low Level Input Voltage
Conditions
V_IN = V_DD
V_IN = 0V
Min Typ Max Units
— — 10 µA
— — -10 µA
2
—
V_DD
V
0
— 0.8 V
LOGIC OUTPUTS
Symbol Parameter
V_OH
High Level Output Voltage
V_IL
Low Level Output Voltage
Conditions
I_OH = -40µA
I_OL = 1mA, V_DD = +5V
I_OL = 0.4mA, V_DD = +3V
Min
V_DD -0.3
—
—
Typ Max Units
——
V
— 0.4
V
— 0.4
V
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V_CC + 1V.
© Catalyst Semiconductor, Inc.
3
Characteristics subject to change without notice
Doc. No. MD-2004 Rev. G