CAT25010 Datasheet, PDF (3/11 Pages) Catalyst Semiconductor – 1K/2K/4K SPI Serial CMOS EEPROM

CAT25010/20/40
PIN CAPACITANCE ⁽¹⁾
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V.
Symbol
Test Conditions
Max.
C_OUT Output Capacitance (SO)
8
C_IN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
Units
pF
pF
Conditions
V_OUT=0V
V_IN=0V
A.C. CHARACTERISTICS
SYMBOL PARAMETER
Limits
1.8V-6.0V 2.5V-6.0V
Min. Max. Min. Max.
4.5V-5.5V
Min. Max.
Test
UNITS Conditions
tSU
Data Setup Time
50
20
20
ns VIH = 2.4V
tH
Data Hold Time
tWH
SCK High Time
tWL
SCK Low Time
50
20
20
250
75
40
250
75
40
ns CL = 100pF
ns VOL = 0.8V
ns VOH = 2.0v
fSCK
tLZ
tRI(1)
tFI(1)
t_HD
t_CD
t_WC(3)
t_V
Clock Frequency
DC
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
100
HOLD Hold Time
100
Write Cycle Time
Output Valid from Clock Low
1 DC
50
2
2
40
40
5
250
5 DC 10 MHz
50
50
ns
2
2
µs
2
2
µs
40
ns
40
ns CC_{L L}==15000ppFF
5
5
ms
(note 2)
75
40
ns
t_HO
Output Hold Time
0
0
0
ns
t_DIS
t_HZ
t_CS
t_CSS
t_CSH
t_WPS
t_WPH
Output Disable Time
HOLD to Output High Z
CS High Time
CS Setup Time
CS Hold Time
WP Setup Time
WP Hold Time
250
75
75
ns
150
50
50
ns
500
100
100
ns
500
100
100
ns
500
100
100
ns
150
50
50
ns
150
50
50
ns
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
Input Pulse Voltages: 0.3V_CC to 0.7V_CC
Input rise and fall times: ≤10ns
Input and output reference voltages: 0.5V_CC
Output load: current source IOL max/IOH max; C_L=50pF
(3) t_WC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
3
Doc. No. 1006, Rev. L