CAT24WC66 Datasheet, PDF (3/10 Pages) Catalyst Semiconductor – 64K-Bit I2C Serial CMOS EEPROM

CAT24WC66
A.C. CHARACTERISTICS
V_CC = +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol Parameter
FSCL
Clock Frequency
T (1)
I
Noise Suppression Time Constant at
SCL, SDA Inputs
t_AA
SCL Low to SDA Data Out and
ACK Out
t ⁽¹⁾
BUF
Time the Bus Must be Free Before a
New Transmission Can Start
t_HD:STA
t_LOW
t_HIGH
t_SU:STA
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a
Repeated Start Condition)
t_HD:DAT
Data In Hold Time
t_SU:DAT
Data In Setup Time
t ⁽¹⁾
R
SDA and SCL Rise Time
t ⁽¹⁾
F
SDA and SCL Fall Time
t_SU:STO
Stop Condition Setup Time
t_DH
Data Out Hold Time
Power-Up Timing ⁽¹⁾⁽²⁾
1.8V - 2.5V
Min
Max
100
200
3.5
4.7
4
4.7
4
4.7
0
50
1
300
4
100
4.5V - 5.5V
Min
Max
400
200
1
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
0.6
100
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Symbol
Parameter
Min
Typ
Max
t_PUR
Power-Up to Read Operation
1
t_PUW
Power-Up to Write Operation
1
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
Write Cycle Limits
Symbol
Parameter
tWR
Write Cycle Time
Min
Typ
Max
10
Units
ms
ms
Units
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
3
Doc. No. 1037, Rev. H