CAT5269 Datasheet, PDF (2/15 Pages) Catalyst Semiconductor – Dual Digitally Programmable Potentiometers (DPP) with 256 Taps and 2-wire Interface

CAT5269
PIN DESCRIPTION
Pin
(SOIC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
NC
A0
NC
NC
NC
NC
VCC
RL0
RH0
RW0
A2
WP
SDA
A1
RL1
RH1
RW1
GND
NC
NC
NC
NC
SCL
A3
Function
No Connect
Device Address, LSB
No Connect
No Connect
No Connect
No Connect
Supply Voltage
Low Reference Terminal for Potentiometer 0
High Reference Terminal for Potentiometer 0
Wiper Terminal for Potentiometer 0
Device Address
Write Protection
Serial Data Input/Output
Device Address
Low Reference Terminal for Potentiometer 1
High Reference Terminal for Potentiometer 1
Wiper Terminal for Potentiometer 1
Ground
No Connect
No Connect
No Connect
No Connect
Bus Serial Clock
Device Address
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT5269 serial clock input pin is used to
clock all data transfers into or out of the device.
SDA: Serial Data
The CAT5269 bidirectional serial data pin is
used to transfer data into and out of the device.
The SDA pin is an open drain output and can be
wire-Ored with the other open drain or open
collector I/Os.
A0, A1, A2, A3: Device Address Inputs
These inputs set the device address when
addressing multiple devices. A total of sixteen
devices can be addressed on a single bus. A
match in the slave address must be made with
the address input in order to initiate communica-
tion with the CAT5269.
R_H, R_L: Resistor End Points
The two sets of R_H and R_L pins are equivalent
to the terminal connections on a mechanical
potentiometer.
RW: Wiper
The RW pins are equivalent to the wiper terminal
of a mechanical potentiometer.
WP: Write Protect Input
The WP pin when tied low prevents non-volatile
writes to the data registers (change of wiper
control register is allowed) and when tied high or
left floating normal read/write operations are
allowed. See Write Protection on page 7 for
more details.
DEVICE OPERATION
The CAT5269 is two resistor arrays integrated with a 2-wire serial interface, two 8-bit wiper control registers and eight
8-bit, non-volatile memory data registers. Each resistor array contains 255 separate resistive elements connected in
series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (R_H and
R_L). The tap positions between and at the ends of the series resistors are connected to the output wiper terminals
(R_W)by a CMOS transistor switch. Only one tap point for each potentiometer is connected to its wiper terminal at a
time and is determined by the value of the wiper control register. Data can be read or written to the wiper control
registers or the non-volatile memory data registers via the 2-wire bus. Additional instructions allow data to be
transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. Also,
the device can be instructed to operate in an "increment/decrement" mode.
Document No. 2123, Rev. B
2