CAT5269 Datasheet, PDF (1/15 Pages) Catalyst Semiconductor – Dual Digitally Programmable Potentiometers (DPP) with 256 Taps and 2-wire Interface

CAT5269
Dual Digitally Programmable Potentiometers (DPP™)
with 256 Taps and 2-wire Interface
FEATURES
ALOGEN ^FR
LEA _{D F REETM}
s Two linear taper digitally programmable poten-
tiometers
s 256 resistor taps per potentiometer
s End to end resistance 50kΩ or 100kΩ
s Potentiometer control and memory access via
2-wire interface (I²C like)
s Low wiper resistance, typically 100Ω
s Nonvolatile memory storage for up to four
wiper settings for each potentiometer
s Automatic recall of saved wiper settings at
power up
s 2.5 to 6.0 volt operation
s Standby current less than 1 µA
s 1,000,000 nonvolatile WRITE cycles
s 100 year nonvolatile memory data retention
s 24-lead SOIC and TSSOP packages
s Industrial temperature range
DESCRIPTION
The CAT5269 is two digitally programmable
potentiometers (DPPs™) integrated with control logic
and 18 bytes of NVRAM memory. Each DPP consists of
a series of resistive elements connected between two
externally accessible end points. The tap points between
each resistive element are connected to the wiper
outputs with CMOS switches. A separate 8-bit control
register (WCR) independently controls the wiper tap
switches for each DPP. Associated with each wiper
control register are four 8-bit non-volatile memory data
registers (DR) used for storing up to four wiper settings.
Writing to the wiper control register or any of the
non-volatile data registers is via a 2-wire serial bus. On
power-up, the contents of the first data register (DR0)
for each of the four potentiometers is automatically
loaded into its respective wiper control registers.
The CAT5269 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40˚C to 85˚C industrial
operating temperature range and offered in a 24-lead
SOIC and TSSOP packages.
PIN CONFIGURATION
SOIC Package (J, W)
TSSOP Package (U, Y)
NC
A0
NC
NC
NC
NC
VCC
R _L0
R _H0
R _W0
A2
WP
1
24
2
23
3
22
4
21
5
20
6 _CAT 19
7 ⁵²⁶⁹ 18
8
17
9
16
10
15
11
14
12
13
A3
SCL
NC
NC
NC
NC
GND
RW1
RH1
R _L1
A1
SDA
FUNCTIONAL DIAGRAM
RH0 RH1
SCL
SDA
2-WIRE BUS
INTERFACE
WIPER
CONTROL
REGISTERS
WP
A0
A1
CONTROL
A2
LOGIC
A3
NONVOLATILE
DATA
REGISTERS
R _W0
R _W1
RL0 RL1
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Document No. 2123, Rev. B