CAT5241 Datasheet, PDF (2/16 Pages) Catalyst Semiconductor – Quad Digitally Programmable Potentiometers (DPP™) with 64 Taps and 2-wire Interface

CAT5241
PIN DESCRIPTION
Pin
(SOIC) Name
Function
1
RW0
Wiper Terminal for Potentiometer 0
2
RL0
Low Reference Terminal for Potentiometer 0
3
RH0
High Reference Terminal for Potentiometer 0
4
A0
Device Address, LSB
5
A2
Device Address
6
RW1
Wiper Terminal for Potentiometer 1
7
RL1
Low Reference Terminal for Potentiometer 1
8
RH1
High Reference Terminal for Potentiometer 1
9
SDA
Serial Data Input/Output
10
GND
Ground
11
RH2
High Reference Terminal for Potentiometer 2
12
RL2
Low Reference Terminal for Potentiometer 2
13
RW2
Wiper Terminal for Potentiometer 2
14
SCL
Bus Serial Clock
15
A3
Device Address
16
A1
Device Address
17
RH3
High Reference Terminal for Potentiometer 3
18
RL3
Low Reference Terminal for Potentiometer 3
19
RW3
Wiper Terminal for Potentiometer 3
20
VCC
Supply Voltage
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT5241 serial clock input pin is used to clock
all data transfers into or out of the device.
SDA: Serial Data
The CAT5241 bidirectional serial data pin is used
to transfer data into and out of the device. The
SDA pin is an open drain output and can be wire-
or'd with the other open drain or open collector
outputs.
A0, A1, A2, A3: Device Address Inputs
These inputs set the device address when ad-
dressing multiple devices. A total of sixteen
devices can be addressed on a single bus. A
match in the slave address must be made with the
address input in order to initiate communication
with the CAT5241.
RH, RL: Resistor End Points
The four sets of RH and RL pins are equivalent to
the terminal connections on a mechanical potenti-
ometer.
RW: Wiper
The four RW pins are equivalent to the wiper
terminal of a mechanical potentiometer.
DEVICE OPERATION
The CAT5241 is four resistor arrays integrated with 2-
wire serial interface logic, four 6-bit wiper control registers
and sixteen 6-bit, non-volatile memory data registers.
Each resistor array contains 63 separate resistive
elements connected in series. The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (R_H and R_L). R_H and R_L are
symmetrical and may be interchanged. The tap positions
between and at the ends of the series resistors are
connected to the output wiper terminals (R_W) by a
CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a time
and is determined by the value of the wiper control
register. Data can be read or written to the wiper control
registers or the non-volatile memory data registers via
the 2-wire bus. Additional instructions allow data to be
transferred between the wiper control registers and
each respective potentiometer's non-volatile data
registers. Also, the device can be instructed to operate
in an "increment/decrement" mode.
Document No. 2011, Rev. J
2