CAT1024_07 Datasheet, PDF (12/20 Pages) Catalyst Semiconductor – Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM and Manual Reset

CAT1024, CAT1025
Acknowledge Polling
Disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host’s write opration, the CAT1024/25 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address for a write operation. If
the device is still busy with the write operation, no
ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can
then proceed with the next read or write operation.
WRITE PROTECTION PIN (WP)
The Write Protection feature (CAT1025 only) allows
the user to protect against inadvertent memory array
programming. If the WP pin is tied to V_CC, the entire
memory array is protected and becomes read only.
The CAT1025 will accept both slave and byte addre-
sses, but the memory location accessed is protected
from programming by the device’s failure to send an
acknowledge after the first byte of data is received.
READ OPERATIONS
The READ operation for the CAT1024/25 is initiated in the
same manner as the write operation with one exception,
the R/¯W¯ bit is set to one. Three different READ operations
are possible: Immediate/Current Address READ,
Selective/Random READ and Sequential READ.
Figure 10. Immediate Address Read Timing
S
T
S
BUS ACTIVIT Y: ^A
SLAVE
T
MASTER ^R ADDRESS
O
T
P
SDA LINE S
P
A
N
C
DATA
O
K
A
C
K
SCL
8
9
SDA
8TH BI T
DATA OUT
NO ACK
STOP
Doc. No. 3008 Rev. N
12
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice