CAT5261 Datasheet, PDF (10/15 Pages) Catalyst Semiconductor – Dual Digitally Programmable Potentiometer

CAT5261
— Write Data Register - write a new value to the
selected Data Register
— Read Status - Read the status of the WIP bit which
when set to "1" signifies a write cycle is in progress.
The basic sequence of the three byte instructions is
illustrated in Figure 8. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be delayed
by tWRL. A transfer from the WCR (current wiper position),
to a Data Register is a write to non-volatile memory and
takes a minimum of tWR to complete. The transfer can
occur between one of the potentiometers and one of its
associated registers; or the transfer can occur between
both potentiometers and one associated register.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the
CAT5261; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
— XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
— XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Figure 7. Two-Byte Instruction Sequence
Control Register to the specified associated
Data Register.
— Global XFR Data Register to Wiper
Control Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control
Registers.
— Global XFR Wiper Counter Register to
Data Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (Figure 9
and 10). The Increment/Decrement command is differ-
ent from the other commands. Once the command is
issued the master can clock the selected wiper up and/
or down in one segment steps; thereby providing a fine
tuning capability to the host. For each SCK clock pulse
(tHIGH) while SI is HIGH, the selected wiper will move one
resistor segment towards the RH terminal. Similarly, for
each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the RL
terminal.
See Instructions format for more detail.
SI
0101 00
ID3 ID2 ID1 ID0 _A3 A2 A1 A0 _{I3 I2 I1 I0 R1 R0 P1 P0}
Device ID
Internal
Address
Instruction
Opcode
Register Pot/WCR
Address Address
Figure 8. Three-Byte Instruction Sequence
SI
0 101
00
ID3 ID2 ID1 ID0 A3 A2 A1 A0 ^I3 I2 ^I1 I0 R1 R0 ^{P1 P0 D7 D6 D5 D4 D3 D2 D1 D0}
Device ID
Internal
Address
Instruction
Opcode
Data Pot/WCR
Register Address
Address
WCR[7:0]
or
Data Register D[7:0]
Figure 9. Increment/Decrement Instruction Sequence
SI
010100
ID3 ID2 ID1 ID0 _{A3 A2 A1 A0 I3 I2} I1 _{I0 R1 R0 P1 P0 I I}
ID
D
Device ID
Internal
Address
NN
NE
E
Instruction Data Pot/WCR C C
CC
C
Opcode
Register ^{Address 1 2}
n1
n
Address
Document No. 2122, Rev. B
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