CAT5132 Datasheet, PDF (10/13 Pages) Catalyst Semiconductor – 15 Volt Digitally Programmable Potentiometer (DPP) with 128 Taps and 2-wire Interface

CAT5132
Data Register (DR)
The Data Register (DR) is a nonvolatile register and its
contents are automatically written to the Wiper Control
Register (WCR) on power-up. It can be read at any time
without effecting the value of the WCR. The DR, like the
WCR, only stores the 7 LSB bits and will report the MSB
bit as a “0”. Writing to the DR is performed in the same
fashion as the WCR except that a time delay of up to 5ms
is experienced while the nonvolatile store operation is
being performed. During the internal non-volatile write
cycle, the device ignores transitions at the SDA and SCL
pins, and the SDA output is at a high impedance state.
The WCR is also written during a write to DR. After a DR
WRITE is complete the DR and WCR will contain the
same wiper position.
To write or read to the DR, first the access to DR is selected, see table 1 then the data is written or read using the
following sequences.
A write operation (see Table 6) requires a Start condition, followed by a valid slave address byte, a valid address byte
00h, a data byte and a STOP condition. After each of the three bytes the CAT5132 responds with an acknowledge.
At this time the data is written both to volatile and non-volatile registers, then the device enters its standby state.
Table 6. DR Write Operation
1st byte
2nd byte
3rd byte
AR address - 02h
DR(00h) selection
ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A 0 0 0 0 0 0 0 0 A SP
slave address byte
DR address - 00h
data byte
ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 0 0 A X X X X X X X X A SP
A read operation (see Table 7) requires a Start condition, followed by a valid slave address byte, a valid address byte
00h, a second Start and a second slave address byte for read. After each of the three bytes the CAT5132 responds
with an acknowledge and then the device transmits the data byte. The master terminates the read operation by issuing
a STOP condition following the last bit of Data byte.
Table 7. DR Read Operation
1st byte
2nd byte
3rd byte
AR address - 02h
DR(00h) selection
ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A 0 0 0 0 0 0 0 0 A SP
slave address byte
DR address - 00h
ST 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 0 0
slave address byte
data byte
ST 0 1 0 1 0 0 0 1 A 0 X X X X X X X
SP
Doc. No. 25092, Rev. 00
10
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice