CAT24WC164 Datasheet, PDF (7/10 Pages) Catalyst Semiconductor – 16K-Bit Serial EEPROM, Cascadable

CAT24WC164
READ OPERATIONS
The READ operation for the CAT24WC164 is initiated in
the same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
Immediate Address Read
The device address counter contains the address of the
last byte accessed, incremented by one. In other words,
if the last READ or WRITE access was to address N, the
READ immediately following would access data from
address N+1. If N=2047, then the counter will 'wrap
around' to addrss 0 and continue to clock out data.
After the CAT24WC164 receives its slave address
information (with the R/W bit set to one), it issues an
acknowledge, then transmits the 8-bit byte requested.
The master device does not send an acknowledge but
will generate a STOP condition.
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24WC164 acknowledge the word
address, the Master device resends the START condition
and the slave address, this time with the R/W bit set to
one. The CAT24WC164 then responds with its
acknowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by
either the immediate Address READ or Selective
READ operations. After the CAT24WC164 sends
initial 8-bit byte requested, the Master will respond
with an acknowledge which tells the device it requires
more data. The CAT24WC164 will continue to output
an 8-bit byte for each acknowledge sent by the Master.
The operation is terminated when the Master fails to
respond with an acknowledge, thus sending the STOP
condition.
The data being transmitted from the CAT24WC164 is
outputted sequentially with data from address N
followed by data from address N+1. The READ
operation address counter increments all of the
CAT24WC164 address bits so that the entire memory
array can be read during one operation. If more than
the 2047 bytes are read out, the counter will “wrap
around” and continue to clock out data bytes.
Figure 6. Byte Write Timing
S
T
BUS ACTIVITY: ^A
MASTER ^R
T
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
DATA
O
P
SDA LINE S
P
A
A
A
C
C
C
K
K
K
Figure 7. Page Write Timing
S
T
BUS ACTIVITY: ^A
MASTER ^R
T
SDA LINE S
SLAVE
ADDRESS
BYTE
ADDRESS (n)
A
A
C
C
K
K
DATA n
DATA n+1
A
A
C
C
K
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
S
T
DATA n+15 ^O
P
P
A
C
K
7
Doc. No. 1026, Rev. I