CAT24WC164 Datasheet, PDF (6/10 Pages) Catalyst Semiconductor – 16K-Bit Serial EEPROM, Cascadable

CAT24WC164
When the CAT24WC164 is in a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT24WC164 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the remainder of the byte address that is to be written into
the address pointer of the CAT24WC164. After receiving
another acknowledge from the Slave, the Master device
transmits the data byte to be written into the addressed
memory location. The CAT24WC164 acknowledge once
more and the Master generates the STOP condition, at
which time the device begins its internal programming
cycle to nonvolatile memory. While this internal cycle is
in progress, the device will not respond to any request
from the Master device.
Page Write
The CAT24WC164 writes up to 16 bytes of data in a
single write cycle, using the Page Write operation. The
Page Write operation is initiated in the same manner as
the Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to fifteen additional bytes. After each byte has
been transmitted the CAT24WC164 will respond with an
acknowledge, and internally increment the low order
address bits by one. The high order bits remain
unchanged.
If the Master transmits more than sixteen bytes prior to
sending the STOP condition, the address counter ‘wraps
around’, and previously transmitted data will be
overwritten.
Once all sixteen bytes are received and the STOP
condition has been sent by the Master, the internal
programming cycle begins. At this point all received data
is written to the CAT24WC164 in a single write cycle.
Acknowledge Polling
The disabling of the inputs can be used to take advantage
of the typical write cycle time. Once the stop condition
is issued to indicate the end of the host’s write operation,
the CAT24WC164 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT24WC164 is still busy
with the write operation, no ACK will be returned. If the
CAT24WC164 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to V_CC, the entire memory array is
protected and becomes read only. The CAT24WC164
will accept both slave and byte addresses, but the
memory location accessed is protected from
programming by the device’s failure to send an
acknowledge after the first byte of data is received.
Figure 5. Slave Address Bits
CAT24WC164 1 A2 A1 A0 a10 a9 a8 R/W
** a8, a9 and a10 correspond to the address of the memory array address word.
*** A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).
Doc. No. 1026, Rev. I
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