CM1215 Datasheet, PDF (6/10 Pages) California Micro Devices Corp – 1-, 2- and 4-Channel Low Capacitance ESD Arrays

PRELIMINARY
CM1215
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against
ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/
Ground rails as well as the signal trace segment
between the signal input (typically a connector) and the
ESD protection device. Refer to Figure 1, which illus-
trates an example of a positive ESD pulse striking an
input channel. The parasitic series inductance back to
the power supply is represented by L1 and L2. The
voltage VCL on the line being protected is:
V_CL = Fwd voltage drop of D₁ + V_SUPPLY +
L1 x d(I_ESD) / dt+ L2 x d(IESD) / dt
where IESD is the ESD current pulse, and VSUPPLY
is the positive supply voltage.
An ESD current pulse can rise from zero to its peak
value in a very short time. As an example, a level 4
contact discharge per the IEC61000-4-2 standard
results in a current pulse that rises from zero to 30
Amps in 1ns. Here d(IESD)/dt can be approximated by
d(_ESD)/dt, or 30/(1x10-9). So just 10nH of series induc-
tance (L1 and L2 combined) will lead to a 300V incre-
ment in VCL!
Similarly for negative ESD pulses, parasitic series
inductance from the V_N pin to the ground rail will lead
to drastically increased negative voltage on the line
being protected.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges. The power supply
bypass capacitor mentioned above should be as close
to the V_P pin of the Protection Array as possible, with
minimum PCB trace lengths to the power supply,
ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See also California Micro Devices Application Note
AP-209, “Design Considerations for ESD Protection”,
in the Applications section at www.calmicro.com.
Figure 3. Application of Positive ESD Pulse between Input Channel and Ground
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