CM1209 Datasheet, PDF (6/9 Pages) California Micro Devices Corp – 4,6 & 8 Channel ESD Protection Arrays with Zener Supply Clamp

CM1209
Application Information
Design Considerations
In order to realize the maximum protection against
ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/
Ground rails as well as the signal trace segment
between the signal input (typically a connector) and the
ESD protection device. Refer to Figure 4, which illus-
trates an example of a positive ESD pulse striking an
input channel. The parasitic series inductance back to
the power supply is represented by L₁ and L₂. The volt-
age V_CL on the line being protected is:
V_CL = Fwd voltage drop of D₁ + V_SUPPLY + L₁ x d(I_ESD ) / dt
+ L₂ x d(I_ESD ) / dt
where I_ESD is the ESD current pulse, and V_SUPPLY is
the positive supply voltage.
An ESD current pulse can rise from zero to its peak
value in a very short time. As an example, a level 4
contact discharge per the IEC61000-4-2 standard
results in a current pulse that rises from zero to 30
Amps in 1ns. Here d(I_ESD)/dt can be approximated by
∆I_ESD/∆t, or 30/(1x10^-9). So just 10nH of series induc-
tance (L₁ and L₂ combined) will lead to a 300V incre-
ment in V_CL!
Similarly for negative ESD pulses, parasitic series
inductance from the V_N pin to the ground rail will lead
to drastically increased negative voltage on the line
being protected.
The CM1209 has an integrated Zener diode between
V_P and V_N. This greatly reduces the effect of supply rail
inductance L₂ on V_CL by clamping V_P at the breakdown
voltage of the Zener diode. However, for the lowest
possible V_CL, especially when V_P is biased at a voltage
significantly below the Zener breakdown voltage, it is
recommended that a 0.22µF ceramic chip capacitor be
connected between V_P and the ground plane.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of
expected electrostatic discharges. The power supply
bypass capacitor mentioned above should be as close
to the V_P pin of the Protection Array as possible, with
minimum PCB trace lengths to the power supply,
ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See California Micro Devices Application Note AP209,
“Design Considerations for ESD Protection", under
Applications at www.calmicro.com.
L₂
POSITIVE SUPPLY RAIL
V_P
PATH OF ESD CURRENT PULSE I_ESD
0.22µF
V_N
D₁
ONE
CHANNEL
D₂
OF
CM1209
L1
CHANNEL
INPUT
20A
0A
LINE BEING
PROTECTED
V_CL
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
GROUND RAIL
CHASSIS GROUND
Figure 4. Application of Positive ESD Pulse between Input Channel and Ground
© 2004 California Micro Devices Corp. All rights reserved.
6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 L Tel: [phone]
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01/09/04