CSPPT Datasheet, PDF (1/4 Pages) California Micro Devices Corp – CHIP SCALE PARALLEL TERMINATION ARRAY

CALIFORNIA MICRO DEVICES
Chip Scale Parallel Termination Array
Features
• 8,16 or 32 integrated high frequency
bussed terminations
• Ultra small footprint Chip Scale Package
• Ceramic substrate
• 0.35mm Eutectic Solder Bumps, 0.65mm pitch
Applications
• Parallel resistive bus termination
• Bussed resistor array
CSPPT
Product Description
The CSPPT is a high performance Integrated Passive
Device (IPD) which provides parallel terminations
suitable for use in high speed bus applications. Eight (8),
sixteen (16), or thirty-two (32) parallel termination
versions are provided. These resistors provide excellent
high frequency performance in excess of 3GHz and are
manufactured to an absolute tolerance as low as ±1%.
The Chip Scale Package provides an ultra small
footprint for this IPD and provides minimal parasitics
compared to conventional packaging. Typical bump
inductance is less than 25pH. The large solder bumps
and ceramic substrate allow for standard attachment to
laminate printed circuit boards without the use of
underfill.
SCHEMATIC DIAGRAMS
B
R1
R1
R1
R1
D
R1
R1
R1
R1
R1
R1
R1
R1
A
1
2
3
4
5
CSPPT08
D
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
C
B
R1
R1
R1
R1
R1
R1
R1
R1
C
B
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
R1
A
1
2
3
4
5
CSPPT16
R1
R1
A
1
2
3
R1
R1
R1
R1
4
5
6
7
8
CSPPT32
R1
R1
9
10
© 2000 California Micro Devices Corp. All rights reserved.
11/10/2000 215 Topaz Street, Milpitas, California 95035
Tel: [phone]
Fax: [phone]
C1290700
www.calmicro.com
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