EP9301 Datasheet, PDF (8/41 Pages) Cirrus Logic – Entry-level ARM9 System-on-chip Processor

EP9301
Entry Level ARM9 System-on-Chip Processor
Universal Asynchronous
Receiver/Transmitters (UARTs)
Two 16550-compatible UARTs are supplied. One
provides asynchronous HDLC (High-level Data Link
Control) protocol support for full duplex transmit and
receive. The HDLC receiver handles framing, address
matching, CRC checking, control-octet transparency, and
optionally passes the CRC to the host at the end of the
packet. The HDLC transmitter handles framing, CRC
generation, and control-octet transparency. The host
must assemble the frame in memory before
transmission. The HDLC receiver and transmitter use the
UART FIFOs to buffer the data streams. The second
UART provides IrDA^® compatibility.
• UART1 supports modem bit rates up to 115.2 kbps,
supports HDLC and includes a 16 byte FIFO for
receive and a 16 byte FIFO for transmit. Interrupts are
generated on Rx, Tx and modem status change.
• UART2 contains an IrDA encoder operating at either
the slow (up to 115 kbps), medium (0.576 or 1.152
Mbps), or fast (4 Mbps) IR data rates. It also has a 16
byte FIFO for receive and a 16 byte FIFO for transmit.
Table F. Universal Asynchronous Receiver/Transmitters Pin
Assignments
Pin Mnemonic
Pin Name - Description
TXD0
RXD0
CTSn
DSRn / DCDn
DTRn
RTSn
EGPIO[0] / RI
TXD1 / SIROUT
RXD1 / SIRIN
UART1 Transmit
UART1 Receive
UART1 Clear To
Send / Transmit Enable
UART1 Data Set
Ready / Data Carrier Detect
UART1 Data Terminal Ready
UART1 Ready To Send
UART1 Ring Indicator
UART2 Transmit / IrDA
Output
UART2 Receive / IrDA Input
Dual Port USB Host
The USB Open Host Controller Interface (Open HCI)
provides full speed serial communications ports at a
baud rate of 12 Mbits/sec. Up to 127 USB devices
(printer, mouse, camera, keyboard, etc.) and USB hubs
can be connected to the USB host in the USB “tiered-
start” topology.
This includes the following feature:
• Compliance with the USB 2.0 specification
• Compliance with the Open HCI Rev 1.0 specification
• Supports both low speed (1.5 Mbps) and full speed
(12 Mbps) USB device connections
• Root HUB integrated with 2 downstream USB ports
• Transceiver buffers integrated, over-current protection
on ports
• Supports power management
• Operates as a master on the bus
The Open HCI host controller initializes the master DMA
transfer with the AHB bus:
• Fetches endpoint descriptors and transfer descriptors
• Accesses endpoint data from system memory
• Accesses the HC communication area
• Writes status and retire transfer descriptor
Table G. Dual Port USB Host Pin Assignments
Pin Mnemonic
Pin Name - Description
USBp[2,0]
USB Positive signals
USBm[2,0]
USB Negative Signals
Note: USBm[1] and USBp[1] are not bonded out.
Two-Wire Interface With EEPROM Support
The two-wire interface provides communication and
control for synchronous-serial-driven devices.
Table H. Two-Wire Port with EEPROM Support Pin Assignments
Pin Mnemonic Pin Name - Description
Alternative
Usage
EECLK
EEDATA
Two-wire Interface Clock
Two-wire Interface Data
General
Purpose I/O
General
Purpose I/O
Real-Time Clock with Software Trim
The software trim feature on the real time clock (RTC)
provides software controlled digital compensation of the
32.768 KHz input clock. This compensation is accurate to
± 1.24 sec/month.
Note: A real time clock must be connected to RTCXTALI or
the EP9301device will not boot.
Table I. Real-Time Clock with Pin Assignments
Pin Mnemonic
Pin Name - Description
RTCXTALI
RTCXTALO
Real-Time Clock Oscillator Input
Real-Time Clock Oscillator Output
8
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