CS4330 Datasheet, PDF (8/38 Pages) Cirrus Logic – 8 Pin Stereo D/A Converter for Digital Audio

CS4330, CS4331, CS4333
SYSTEM DESIGN
The CS4330/31/33 accept data at standard audio
frequencies including 48 kHz, 44.1 kHz and
32 kHz. Audio data is input via the serial data
input pin (SDATA). The Left/Right Clock
(LRCK) defines the channel and delineation of
data and the Serial Clock (SCLK) clocks audio
data into the input data buffer. The CS4330,
CS4331 and CS4333 differ in the serial data for-
mat as shown in Figures 4-7. The Master Clock
(MCLK) is used to operate the digital interpola-
tion filter and the delta-sigma modulator.
Master Clock
The MCLK must be either 256×, 384×, or 512×
the desired input sample rate, Fs. Fs is the fre-
quency at which words for each channel are
input to the digital-to-analog converter, and is
equal to the LRCK frequency. The MCLK to
LRCK frequency ratio is detected automatically
during the initialization sequence by counting
the number of MCLK transitions during a single
LRCK period. Internal dividers are set to gener-
ate the proper clocks for the digital filter,
delta-sigma modulator and switched-capacitor
filter. Table 1 illustrates several standard audio
sample rates and the required MCLK and LRCK
frequencies.
LRCK
(kHz)
32
44.1
48
MCLK (MHz)
256x
384x
512x
8.1920 12.2880 16.3840
11.2896 16.9344 22.5792
12.2880 18.4320 24.5760
Table 1. Common Clock Frequencies
Serial Clock
The serial clock controls the shifting of data into
the input data buffers. The CS4330/31/33 sup-
port both external and internal serial clock
generation modes. Refer to Figures 4-7 for data
formats.
External Serial Clock Mode
The CS4330/31/33 will enter the External Serial
Clock Mode when 4 low to high transitions are
detected on the DEM/SCLK pin during any
phase of the LRCK period. When this mode is
enabled, the Internal Serial Clock Mode and de-
emphasis filter cannot be accessed. The
CS4330/31/33 must return to Power-Down to
exit this mode. Refer to Figure 8.
Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial
clock is internally derived and synchronous with
MCLK and LRCK. The SCLK/LRCK frequency
ratio is either 32, 48, or 64. Operation in this
mode is identical to operation with an external
serial clock synchronized with LRCK. This
mode allows access to the digital de-emphasis
function. Refer to Figure 8.
While the Internal Serial Clock Mode is pro-
vided to allow access to the de-emphasis filter,
the Internal Serial Clock Mode also eliminates
possible clock interference from an external
SCLK. Use of Internal Serial Clock Mode is al-
ways preferred, even when de-emphasis filtering
is not required.
De-Emphasis
The CS4330/31/33 include on-chip digital de-
emphasis. Figure 3 shows the de-emphasis curve
for Fs equal to 44.1 kHz. The frequency re-
sponse of the de-emphasis curve will scale
proportionally with changes in sample rate, Fs.
The de-emphasis filter is active (inactive) if the
DEM/SCLK pin is low (high) for 8 consecutive
falling edges of LRCK. This function is available
only in the internal serial clock mode.
8
DS136F1