BUF16820 Datasheet, PDF (8/30 Pages) Burr-Brown (TI) – 14-Channel GAMMA VOLTAGE GENERATOR with Programmable VCOM Outputs and OTP Memory

BUF16820
SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006
ACQUIRE OF OTP MEMORY
A general acquire command updates all registers and
DAC outputs to the values stored in OTP memory.
A single channel acquire command updates only the
register and DAC output of the DAC corresponding to the
DAC address used in the command.
General Acquire Command
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF16820 will acknowledge this byte.
3. Send a DAC address byte. Bits D7−D5 must be set
to 100. Bits D4−D0 are any valid DAC address.
Only addresses 00000 to 01101, 10010, 10011, and
10100 are valid and will be acknowledged. Table 3
shows the DAC addresses.
4. Send a STOP condition on the bus.
Following this command, all DAC registers and DAC
outputs change to the OTP memory values.
Single Channel Acquire Command
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF16820 will acknowledge this byte.
3. Send a DAC address byte using the DAC address
corresponding to the DAC output and register to
update with the OTP memory value. Bits D7−D5
must be set to 010. Bits D4−D0 denote the address.
Only addresses 00000 to 01101, 10010, 10011, and
10100 are valid and will be acknowledged. Table 3
shows the DAC addresses.
4. Send a STOP condition on the bus.
See Figure 12 for the timing diagrams for the acquire
commands.
Table 3. DAC Register Addresses
DAC
ADDRESS
DAC_1
DAC_2
DAC_3
DAC_4
DAC_5
DAC_6
DAC_7
DAC_8
DAC_9
DAC_10
DAC_11
DAC_12
DAC_13
DAC_14
V_COM1
V_COM2
Write Disable Bit
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
10010
10011
10100
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READ/WRITE OPERATIONS
Single or mutiple read and write operations can be done in
a single communication transaction. Writing to a DAC
register differs from writing to the OTP memory. Bits
D15−D14 of the most significant byte of data determine if
data will be written to the DAC register or the OTP memory.
See Figure 9 through Figure 11 for the timing diagrams
and requirements for read/write commands.
Read/Write: DAC register
The BUF16820 is able to read from a single DAC or
multiple DACs, or write to the register of a single DAC or
multiple DACs in a single communication transaction.
DAC addresses begin with 00000 (corresponding to
DAC_1) and continue through 01101 (corresponding to
DAC_14). Addresses 10010 and 10011 correspond to
V_COM1 and V_COM2, respectively. Address 10100
corresponds to the write disable bit.
Write commands are performed by setting the read/write
bit LOW. Setting the read/write bit HIGH performs a read
transaction.
Writing:
To write to a single DAC register:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF16820 will acknowledge this byte.
3. Send the DAC or write disable bit address byte. Bits
D7−D5 must be set to 0. Bits D4−D0 denote the
address. Only addresses 00000 to 01101, 10010,
10011, and 10100 are valid and will be
acknowledged. Table 3 shows the DAC addresses.
4. Send two bytes of data for the specified register. Begin
by sending the most significant byte first (bits D15−D8,
of which only bits D9 and D8 are used, and bits
D15−D14 must not be 01), followed by the least
significant byte (bits D7−D0). For address 10100, only
D0 has meaning. This bit is the write disable bit. The
register is updated after receiving the second byte.
5. Send a STOP condition on the bus.
The BUF16820 acknowledges each data byte. If the
master terminates communication early by sending a
STOP or START condition on the bus, the specified
register will not be updated. Updating the DAC register is
not the same as updating the DAC output voltage; see the
Output Latch section.
The process of updating multiple DAC registers begins the
same as when updating a single register. However,
instead of sending a STOP condition after writing the
addressed register, the master continues to send data for
the next register. The BUF16820 automatically and
sequentially steps through subsequent registers as
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