BUF16820 Datasheet, PDF (10/30 Pages) Burr-Brown (TI) – 14-Channel GAMMA VOLTAGE GENERATOR with Programmable VCOM Outputs and OTP Memory

BUF16820
SBOS356A − FEBRUARY 2006 − REVISED OCTOBER 2006
Write: OTP Memory for the DAC Register
The BUF16820 is able to write to the OTP memory of a
single DAC, or multiple DACs in a single communication
transaction. DAC addresses begin with 00000 (corre-
sponding to DAC_1) through 01101 (corresponding to
DAC_14). Addresses 10010 and 10011 correspond to
V_COM1 and V_COM2, respectively. Address 10100 corre-
sponds to the write disable bit.
When programming the OTP memory, the analog supply
voltage must be between 8.5V and 18V.
Write commands are performed by setting the read/write
bit LOW.
To write to a single OTP register:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF16820 will acknowledge this byte.
3. Send the DAC address byte. Bits D7−D5 must be set
to 0. Bits D4−D0 are the DAC address. Only
addresses 00000 to 01101, 10010, 10011, and
10100 are valid and will be acknowledged. Table 3
shows the DAC addresses.
4. Send two bytes of data for the OTP register of the
specified DAC. Begin by sending the most significant
byte first (bits D15−D8, of which only bits D9 and D8
are data bits, and bits D15−D14 must be 01), followed
by the least significant byte (bits D7−D0). For address
10100, only D0 has meaning. This bit is the write
disable bit. The register is updated after receiving the
second byte.
5. Send a STOP condition on the bus.
The BUF16820 will acknowledge each data byte. If the
master terminates communication early by sending a
STOP or START condition on the bus, the specified OTP
register will not be updated. Writing to an OTP register also
updates the DAC register and output voltage.
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To write to multiple OTP registers:
1. Send a START condition on the bus.
2. Send the device address and read/write bit = LOW.
The BUF16820 will acknowledge this byte.
3. Send either the DAC_1 address byte to start at the
OTP register of the first DAC, or send the address byte
for whichever DAC will be the first in the sequence to
be updated. The BUF16820 will begin with the OTP
register of this DAC and step through subsequent
registers in sequential order.
4. Send the bytes of data. Begin by sending the most
significant byte (bits D15−D8, of which only bits D9
and D8 have meaning, and bits D15−D14 must be 01),
followed by the least significant byte (bits D7−D0). The
first two bytes are for the OTP register of the DAC
addressed in step 3. This OTP register is
automatically updated after receiving the second byte.
The next two bytes are for the OTP register of the
following DAC (bits D15−D14 must again be 01). That
DAC OTP register is updated after receiving the fourth
byte. This process continues until the registers of all
following DAC OTP registers have been updated. The
BUF16820 will continue to accept data for a total of 20
DACs; however, the four data sets following the 14th
data set will be meaningless. The 19th and 20th data
sets will apply to V_COM1 and V_COM2. The write disable
bit cannot be accessed using this method. It must be
written to using the write to a single OTP register
procedure.
5. Send a STOP condition on the bus.
The BUF16820 will acknowledge each byte. To terminate
communication, send a STOP or START condition on the
bus. Only DAC registers that have received both bytes of
data are programmed.
OTP WRITE DISABLE
Writing a ‘1’ in bit D0 of register 10100 disables all future
writes. The state of this bit can be accessed the same as
any other data bit. It is important to set this bit to ‘1’ after
the OTP registers have been programmed in order to
prevent accidental changes to the OTP registers. Until bit
D0 of register 10100 is set to ‘1’, any OTP register bit can
be changed from ‘0’ to ‘1’; however, once a bit is set to a
‘1’, it cannot be set back to ‘0’.
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