ADC7802 Datasheet, PDF (8/13 Pages) Burr-Brown (TI) – Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER

TRANSPARENT MODE
This is the default mode for ADC7802. In this mode, the
conversion decisions from the successive approximation
register are latched into the output register as they are made.
Thus, the High byte (the 4 MSBs) can be read after the end
of the ninth clock cycle (five clock cycles for the mux
settling, sample acquisition and auto-zeroing of the compara-
tor, followed by the four clock cycles for the 4MSB deci-
sions.) The complete 12-bit data is available after BUSY has
gone HIGH, or the internal status flag goes LOW (D7 when
HBE is HIGH).
LATCHED OUTPUT MODE
This mode is activated by writing a HIGH to D0 and LOWs
to D1 to D7 in the Special Function Register with CS and WR
LOW and SFR and HBE HIGH. (See the discussion of the
Special Function Register below.)
In this mode, the data from a conversion is latched into the
output buffers only after a conversion is complete, and
remains there until the next conversion is completed. The
conversion result is valid during the next conversion. This
allows the data to be read even after a new conversion is
started, for faster system throughput.
TIMING CONSIDERATIONS
Table I and Figures 3 through 8 show the digital timing of
ADC7802 under the various operating modes. All of the
critical parameters are guaranteed over the full –40^oC to
+85^oC operating range for ease of system design.
SPECIAL FUNCTION REGISTER (SFR)
An internal register is available, either to determine addi-
tional data concerning the ADC7802, or to write additional
instructions to the converter. Access to the Special Function
Register is made by driving SFR HIGH.
SYMBOL
PARAMETER ⁽¹⁾
MIN
TYP
MAX
UNITS
t₁
CS to WR Setup Time ⁽²⁾
0
0
0
ns
t₂
WR or CAL Pulse Width
100
ns
t₃
CS to WR Hold Time ⁽²⁾
0
0
0
ns
t₄
WR to BUSY Propagation Delay
20
50
150
ns
t₅
A0, A1, HBE, SFR Valid to WR Setup Time
0
ns
t₆
A0, A1, HBE, SFR Valid to WR Hold Time
20
ns
t₇
BUSY to CS Setup Time
0
ns
t₈
CS to RD Setup Time ⁽²⁾
0
0
0
ns
t₉
RD Pulse Width
100
ns
t₁₀
CS to RD Hold Time ⁽²⁾
0
0
0
ns
t₁₁
HBE, SFR to RD Setup Time
50
ns
t₁₂
HBE, SFR to RD Hold Time
0
ns
t₁₃
RD to Valid Data (Bus Access Time) ⁽³⁾
80
150
ns
t₁₄
RD to Hi-Z Delay (Bus Release Time) ⁽³⁾
90
180
ns
t₁₅
RD to Hi-Z Delay For SFR ⁽³⁾
20
60
ns
t₁₆
Data Valid to WR Setup Time
100
ns
t₁₇
Data Valid to WR Hold Time
20
ns
NOTES: (1) All input control signals are specified with t_RISE = t_FALL = 20ns (10% to 90% of 5V) and timed from a voltage level of 1.6V. Data is timed from V_IH,
V_IL, V_OH or V_OL. (2) The internal RD pulse is performed by a NOR wiring of CS and RD. The internal WR pulse is performed by a NOR wiring of CS and WR.
(3) Figures 7 and 8 show the measurement circuits and pulse diagrams for testing transitions to and from Hi-Z states.
TABLE I. Timing Specifications (CLK = 1MHz external, T_A = –40°C to +85°C).
CS
t₁
WR
t₅
HBE
SFR
D0 - D7
t₂
t₃
t₆
V_IH
Valid Data
V_IL
t₁₆
t₁₇
FIGURE 5. Writing to the SFR.
CS
RD
SFR
HBE
D0–D7
t₈
t₁₁
t₁₁
t₁₃
t₁₀
t₁₂
t₁₂
t₁₄
SFR Data
FIGURE 6. Reading the SFR.
®
ADC7802
8