ADC7802 Datasheet, PDF (12/13 Pages) Burr-Brown (TI) – Autocalibrating, 4-Channel, 12-Bit ANALOG-TO-DIGITAL CONVERTER

The clock generator can operate between 100kHz and 2MHz.
With R = 100kΩ, the clock frequency will nominally be
800kHz. The internal clock oscillators may vary by up to
20% from device to device, and will vary with temperature,
as shown in the typical performance curves. Therefore, use
of an external clock source is preferred in many applications
where control of the conversion timing is critical, or where
multiple converters need to be synchronized.
APPLICATIONS
BIPOLAR INPUT RANGES
Figure 12 shows a circuit to accurately and simply convert a
bipolar ±5V input signal into a unipolar 0 to 5V signal for
conversion by the ADC7802, using a precision, low-cost
complete difference amplifier, INA105.
INA105
25kΩ ₂
25kΩ ₅
±5V ¹
Input
25kΩ
25kΩ
3
+5V (V_REF+)
FIGURE 12. ±5V Input Range.
0 to 5V
6
to ADC7802
Figure 13 shows a circuit to convert a bipolar ±10V input
signal into a unipolar 0 to 5V signal for conversion by the
ADC7802. The precision of this circuit will depend on the
matching and tracking of the three resistors used.
±10V
Input
+5V
(V +)
REF
R₂
R₁
5kΩ
OPA27
10kΩ
R₃ 10kΩ
0 to 5V
to ADC7802
FIGURE 13. ±10V Input Range.
To trim this circuit for full 12-bit precision, R2 and R3 need
to be adjustable over appropriate ranges. To trim, first have
the ADC7802 converting continually and apply +9.9927V
(+10V – 1.5LSB) at the input. Adjust R3 until the ADC7802
output toggles between the codes FFE hex and FFF hex. This
makes R3 extremely close to R1. Then, apply –9.9976V (–10V
+ 0.5LSB) at the input, and adjust R2 until the ADC7802
output toggles between 000 hex and 001 hex. At each trim
point, the current through the third resistor will be almost
zero, so that one trim iteration will be enough in most cases.
More iterations may be required if the op amp selected has
large offset voltage or bias currents, or if the +5V reference
is not precise.
This circuit can also be used to adjust gain and offset errors
due to the components preceding the ADC7802, to match the
performance of the self-calibration provided by the con-
verter.
INTERFACING TO MOTOROLA
MICROPROCESSORS
Figure 14 shows a typical interface to Motorola microproces-
sors, while Figure 15 shows how the result can be placed in
register D0.
A1 - A23
(A0 - A19)
MC68000
(MC68008)
AS
DACK
R/W
Address Bus
A1
INT
Address ADC_CS
Decoder
Logic
HBE SFR BUSY
CS
RD
DO 0 - DO 7 DO 0
WR
ADC7802
DO 1 D0 - D7
A1
A0
FIGURE 14. Interface to Motorola Microprocessors.
Conversion is initiated by a write instruction decoded by the
address decoder logic, with the lower two bits of the address
bus selecting an ADC input channel, as follows:
MOVE.W D0, ADC-ADDRESS
The result of the conversion is read from the data bus by a
read instruction to ADC-ADDRESS as follows:
MOVEP.W $000 (ADC-ADDRESS), D0
This puts the 12-bit conversion result in the DO register, as
shown in Figure 15. The address decoder must pull down
ADC_CS at ADC-ADDRESS to access the Low byte and
ADC-ADDRESS +2 to access the High byte.
INTERFACING TO INTEL MICROPROCESSORS
Figure 16 shows a typical interface to Intel.
A conversion is initiated by a write instruction to address
ADC_CS. Data pins DO0 and DO1 select the analog input
channel. The BUSY signal can be used to generate a micro-
processor interrupt (INT) when the conversion is completed.
A read instruction from the ADC_CS address fetches the
Low byte, and a read instruction from the ADC_CS address
+2 fetches the High byte.
®
ADC7802
12