CS4205 Datasheet, PDF (74/80 Pages) Cirrus Logic – CrystalClear Audio Codec 97 with Portable Computing

CS4205
GPIO4/SDI3 - General Purpose I/O / Serial Data Input 3, Input/Output, Pin 41
This pin is a general purpose I/O pin that can be used to interface with various external circuitry. When
configured as an input, it functions as a Schmitt triggered input with 350 mV hysteresis at 5 V and 220
mV hysteresis at 3.3 V. When configured as an output, it can function as a normal CMOS output (4 mA
drive) or as an open drain output. This pin also receives the serial data for the third serial input port
when the SDI3 bit in the Serial Port Control Register (Index 6Ah) is ‘set’. This bit powers up in the high
impedance state for backward compatibility.
ZLRCLK - ZV Port Left-Right Clock, Input, Pin 32
This pin receives the Left/Right clock for the Zoomed Video Port. The L/R clock determines which
channel is currently being inputted on the ZSDATA pin. The signal must conform to the ZV Port
Specification.
ZSDATA - ZV Port Serial Data, Input, Pin 33
This pin receives two’s complement MSB-first serial audio data for the Zoomed Video Port. The data is
clocked into the CS4205 by the ZSCLK, and the channel is determined by ZLRCLK. The signal must
conform to the ZV Port Specification.
ZSCLK - ZV Port Serial Clock, Input, Pin 34
This pin receives the serial clock for the Zoomed Video port. The serial clock is used to clock data on
the ZSDATA pin into the CS4205. The signal must conform to the ZV Port Specification.
Power Supply Pins
DVdd1, DVss1 - Digital Supply Voltage 1 / Digital Ground 1, Pins 1 and 4
These pins provide the supply voltage and ground for the clocking section of the CS4205. In XTAL or
OSC clocking modes DVdd1 should be tied to +5 VD or to +3.3 VD, with DVss1 tied to DGND. In PLL
clocking mode, DVdd1 must be tied to +5 VA and DVss1 must be tied to AGND. If connecting these
pins to +5 VD or to +3.3 VD and DGND, the CS4205 and controller AC-link should share a common
digital supply.
DVdd2, DVss2 - Digital Supply Voltage 2 / Digital Ground 2, Pins 9 and 7
These pins provide the digital supply voltage and digital ground for the AC-link section of the CS4205.
In all clocking modes DVdd2 should be tied to +5 VD or to +3.3 VD, with DVss2 tied to DGND. The
CS4205 and controller AC-link should share a common digital supply. DVss2 should be isolated from
analog ground currents.
AVdd1, AVss1 - Analog Supply Voltage 1 / Analog Ground 1, Pins 25 and 26
These pins provide the analog supply voltage and analog ground for the analog and mixed signal
sections of the CS4205. AVdd1 must be tied to the +5 VA power supply, with AVss1 connected to
AGND. It is strongly recommended the +5 VA power supply be generated from a voltage regulator to
ensure proper supply currents and noise immunity from the rest of the system. AVss2 should be isolated
from digital ground currents
AVdd2, AVss2 - Analog Supply Voltage 2 / Analog Ground 2, Pins 38 and 42
The AVdd2 and AVss2 pins are not used on the CS4205 and may be left floating or tied to +5 VA and
AGND for backwards compatibility
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