CS4205 Datasheet, PDF (72/80 Pages) Cirrus Logic – CrystalClear Audio Codec 97 with Portable Computing

CS4205
AC-Link Pins
RESET# - AC ’97 Chip Reset, Input, Pin 11
This active low signal is the asynchronous Cold Reset input to the CS4205. The CS4205 must be reset
before it can enter normal operating mode.
SYNC - AC-Link Serial Port Sync pulse, Input, Pin 10
SYNC is the serial port timing signal for the AC-link. Its period is the reciprocal of the maximum sample
rate, 48 kHz. The signal is generated by the controller and is synchronous to BIT_CLK. SYNC is an
asynchronous input when the CS4205 is configured as a primary codec and is in a PR4 powerdown
state. A series terminating resistor of 47 Ω should be connected on this signal close to the controller.
BIT_CLK - AC-Link Serial Port Master Clock, Input/Output, Pin 6
This input/output signal controls the master clock timing for the AC-link. In primary mode, this signal is a
12.288 MHz output clock derived from either a 24.576 MHz crystal or from the internal PLL based on
the XTL_IN input clock. When the CS4205 is in secondary mode, this signal is an input which controls
the AC-link serial interface and generates all internal clocking including the AC-link serial interface
timing and the analog sampling clocks. A series terminating resistor of 47 Ω should be connected on
this signal close to the CS4205 in primary mode or close to the BIT_CLK source in secondary mode.
SDATA_OUT - AC-Link Serial Data Input Stream to AC ’97, Input, Pin 5
This input signal receives the control information and digital audio output streams. The data is clocked
into the CS4205 on the falling edge of BIT_CLK. A series terminating resistor of 47 Ω should be
connected on this signal close to the controller.
SDATA_IN - AC-Link Serial Data Output Stream from AC ’97, Output, Pin 8
This output signal transmits the status information and digital audio input streams from the ADCs. The
data is clocked out of the CS4205 on the rising edge of BIT_CLK. A series terminating resistor of 47 Ω
should be connected on this signal close to the CS4205.
Clock and Configuration Pins
XTL_IN - Crystal Input/Clock Input, Pin 2
This pin requires either a 24.576 MHz crystal, with the other pin attached to XTL_OUT, or an external
CMOS clock. XTL_IN must have a crystal or clock source attached for proper operation except when
operating in secondary codec mode. The crystal frequency must be 24.576 MHz and designed for
fundamental mode, parallel resonance operation. If an external CMOS clock is used to drive this pin, it
must run at one of these acceptable frequencies: 14.31818. 24.576, 27, or 48 MHz. When configured as
a secondary codec, all timing is derived from the BIT_CLK input signal and this pin should be left
floating. See Section 11, Clocking, for additional details.
XTL_OUT - Crystal Output/ PLL Loop Filter, Pin 3
This pin is used for a crystal placed between this pin and XLT_IN. If an external 24.576 MHz clock is
used on XTL_IN, this pin must be left floating with no traces or components connected to it. If one of
the other acceptable clocks is used on XTL_IN, this pin must be connected to a loop filter circuit. See
Section 11, Clocking, for additional details.
ID1#, ID0# - Codec ID, Inputs, Pins 45 and 46
These pins select the Codec ID for the CS4205, as well as determine the rate of the incoming clock in
PLL mode. They are only sampled after the rising edge of RESET#. These pins are internally pulled up
to the digital supply voltage and should be left floating for logic ‘0’ or tied to digital ground for logic ‘1’.
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