BUF08800 Datasheet, PDF (7/23 Pages) Burr-Brown (TI) – Programmable Reference Generator and 400mA VCOM Driver

BUF08800
www.ti.com
TWO-WIRE BUS OVERVIEW
The BUF08800 communicates through an
industry-standard, two-wire interface to receive data in
slave mode. This standard uses a two-wire, open-drain
interface that supports multiple devices on a single bus.
Bus lines are driven to a logic low level only. The device
that initiates the communication is called a master, and the
devices controlled by the master are slaves. The master
generates the serial clock on the clock signal line (SCL),
controls the bus access, and generates the START and
STOP conditions.
To address a specific device, the master initiates a START
condition by pulling the data signal line (SDA) from a HIGH
to LOW logic level while SCL is HIGH. All slaves on the bus
shift in the slave address byte, with the last bit indicating
whether a read or write operation is intended. During the
ninth clock pulse, the slave being addressed responds to
the master by generating an Acknowledge and pulling
SDA LOW.
Data transfer is then initiated and 8 bits of data are sent
followed by an Acknowledge Bit. During data transfer,
SDA must remain stable while SCL is HIGH. Any change
in SDA while SCL is HIGH will be interpreted as a START
or STOP condition.
Once all data has been transferred, the master generates
a STOP condition indicated by pulling SDA from LOW to
HIGH while SCL is HIGH.
The BUF08800 can act only as a slave device; therefore,
it never drives SCL. SCL is an input only for the BUF08800.
ADDRESSING THE BUF08800
The address of the BUF08800 is 111010x, where x is the
state of the A0 pin. When the A0 pin is LOW, the device
acknowledges on address 74h (1110100). If the A0 pin is
HIGH, the device acknowledges on address 75h
(1110101), as shown in Table 1.
Other valid addresses are possible through a simple mask
change. Contact your TI representative for information.
Table 1. BUF08800 Bus Address Options
BUF08800 ADDRESS
A0 pin is LOW
(device will not acknowledge on address 74h)
A0 pin is HIGH
(device will acknowledge on address 74h)
ADDRESS
111 0100
111 0101
SBOS380A − FEBRUARY 2007 − REVISED MAY 2007
DATA RATES
The two-wire bus operates in one of three speed modes:
D Standard: allows a clock frequency of up to 100kHz;
D Fast: allows a clock frequency of up to 400kHz; and
D High-speed mode (also called Hs mode): allows a
clock frequency of up to 3.4MHz.
The BUF08800 is fully compatible with all three modes. No
special action is required to use the device in Standard or
Fast modes, but High-speed mode must be activated. To
activate High-speed mode, send a special address byte of
00001xxx, with SCL = 400kHz, following the START
condition; xxx are bits unique to the Hs-capable master,
and can be any value. The BUF08800 responds to the
High-speed mode command regardless of the value of
these last three bits. This byte is called the Hs master
code. (Note that this is different from normal address
bytes—the low bit does not indicate read/write status.) The
BUF08800 does not acknowledge this byte; the
communication protocol prohibits acknowledgment of the
Hs master code. On receiving a master code, the
BUF08800 switches on its Hs mode filters, and
communicates at up to 3.4MHz. Additional high-speed
transfers may be initiated without resending the Hs mode
byte by generating a repeat START without a STOP. The
BUF08800 switches out of Hs mode at the first occurrence
of a STOP condition.
GENERAL CALL RESET AND POWER-UP
The BUF08800 responds to a General Call Reset, which
is an address byte of 00h (0000 0000) followed by a data
byte of 06h (0000 0110). The BUF08800 acknowledges
both bytes. Upon receiving a General Call Reset, the
BUF08800 performs a full internal reset, as though it had
been powered off and then on. It always acknowledges the
General Call address byte of 00h (0000 0000), but does
not acknowledge any General Call data bytes other than
06h (0000 0110).
The BUF08800 automatically performs a reset upon
power-up. As part of the reset, the BUF08800 is configured
for all outputs to change to mid-value, V_S/2.
The BUF08800 resets all outputs to mid-value (V_S/2) when
the device address is sent, followed by a valid DAC
address with bits D7 to D5 set to ‘100’. If these bits are set
to ‘010’, only the DAC being addressed in this most
significant byte and the following least significant byte will
be reset.
COMMAND
General Call Reset
High-Speed Mode
Table 2. Quick-Reference Table of Commands
CODE
Address byte of 00h (0000 0000) followed by a data byte of 06h (0000 0110).
00001xxx, with SCL ≤ 400kHz; where xxx are bits unique to the Hs-capable master.
This byte is called the Hs master code.
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