SRC4392 Datasheet, PDF (55/79 Pages) Burr-Brown (TI) – Two-Channel, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver and Transmitter

SRC4392
www.ti.com
SBFS029B – DECEMBER 2005 – REVISED APRIL 2006
TXIS[1:0]
Transmitter Input Data Source
These bits are used to select the audio data source for the DIT function block.
TXIS1
TXIS0
Output Word Length
0
0
Port A (Default)
0
1
Port B
1
0
DIR
1
1
SRC
TXDIV[1:0]
Transmitter Master Clock Divider
These bits are used to select the Transmitter master clock divider, which determines the output frame rate.
TXDIV1
TXDIV0
Clock Divider
0
0
Divide the master clock by 128. (Default)
0
1
Divide the master clock by 256.
1
0
Divide the master clock by 384.
1
1
Divide the master clock by 512.
TXCLK
Transmitter Master Clock Source
This bit is used to select the master clock source for the Transmitter block.
TXCLK
Transmitter Master Clock Source
0
MCLK Input (Default)
1
RXCKO; the recovered master clock from the DIR function block.
Bit 7 (MSB)
BYPMUX1
TXOFF
TXMUTE
AESOFF
TXBTD
Bit 6
BYPMUX0
Register 08: Transmitter Control Register 2
Bit 5
Bit 4
Bit 3
Bit 2
AESMUX
LDMUX
TXBTD
AESOFF
Bit 1
TXMUTE
Bit 0 (LSB)
TXOFF
Transmitter Line Driver Output Enable
This bit is used to enable or disable the TX+ (pin 32) and TX– (pin 31) line driver outputs.
TXOFF
Transmitter Line Driver
0
Enabled; the line driver outputs function normally. (Default)
1
Disabled; the line driver outputs are forced low.
Transmitter Audio Data Mute
This bit is used to set the 24 bits of audio and auxiliary data to all zeros for both Channels 1 and 2.
TXMUTE
Transmitter Audio Data Mute
0
Disabled (Default)
1
Enabled; the audio data for both Channels 1 and 2 are set to all zeros.
AESOUT Output Enable
This bit is used to enable or disable the AESOUT (pin 34) buffered AES3-encoded CMOS logic level output.
AESOFF
AESOUT Output
0
Enabled; the AESOUT pin functions normally. (Default)
1
Disabled; the AESOUT pin is forced low.
Transmitter C and U Data Buffer Transfer Disable
This bit is used to enable and disable buffer transfers between the DIT User Access (UA) and DIT Transmitter Access (TA) buffers for
both channel status (C) and user (U) data.
Buffer transfers may be disabled, allowing the user to write new C and U data to the UA buffers via the SPI or I²C serial host interface.
Once updated, UA-to-TA buffer transfers may then be re-enabled, allowing the TA buffer to be updated and the new C and U data to be
transmitted at the start of the next block.
TXBTD
User Access (UA) to Transmitter Access (TA) Buffer Transfers
0
Enabled (Default)
1
Disabled; allows the user to update DIT C and U data buffers.
Note: The TXCUS0 and TXCUS1 bits in control register 0x09 must be set to a non-zero value in order for DIT UA buffer updates to occur.
Submit Documentation Feedback
55