DSP101 Datasheet, PDF (5/22 Pages) Burr-Brown (TI) – DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS

TYPICAL DSP102 FFT SETUP
Brüel & Kjaer
Model 1049 ^1kHz
Digital Signal _±2.75V
Generator
6 Pole,
150kHz
Low-Pass
Filter
1/2
OPA2604
1/2
OPA2604
150Ω
150Ω
DSP102
27 _REF
0.1µF
220pF
2
VINA
CASC ²²
SSF ¹²
13
OSC1
CLKOUT ¹¹
1
+
VPOTA
10
CLKIN
10µF
+5V
16MHz TTL Oscillator
÷80 ÷2
220pF
25
VINB
26
CONV
XCLK
VPOTB SYNC
+
10µF
SOUTA
21 200kHz
16 8MHz
15
20
Burr-Brown
ZPB34
DSP
Processor
FFT
Software
ABSOLUTE MAXIMUM RATINGS
V_A+ to Analog Common .................................................................... +7V
V_A– to Analog Common .................................................................... –7V
V_D to Digital Common ........................................................................ +7V
Analog Common to Digital Common ................................................... ±1V
Control Inputs to Digital Common ............................... –0.5 to V_D + 0.5V
Analog Input Voltage .......................................................................... ±5V
Maximum Junction Temperature .................................................... 150^oC
Internal Power Dissipation ............................................................. 825mW
Lead Temperature (soldering, 10s) ............................................... +300^oC
Thermal Resistance, θ_JA, Plastic DIP ............................................ 50^oC/W
DSP101 PIN CONFIGURATION
Top View
VPOT 1
VIN 2
MSB 3
VOS 4
VA – 5
VA+ 6
DGND 7
DGND 8
V_D 9
CLKIN 10
CLKOUT 11
SSF 12
OSC1 13
OSC2 14
DSP101
DIP
28 AGND
27 REF
26 CAP
25
24
23
22 DGND
21 CONV
20 SOUT
19
18 TAG
17
16 XCLK
15 SYNC
DSP101 PIN ASSIGNMENTS
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NAME
VPOT
VIN
MSB
VOS
V_A–
V_A+
DGND
DGND
V_D
CLKIN
CLKOUT
SSF
OSC1
OSC2
SYNC
XCLK
TAG
SOUT
CONV
DGND
CAP
REF
AGND
DESCRIPTION
Trim Reference Out. 10µF Tantalum to AGND.
Voltage on this pin is approximately 2.75V.
Analog In.
MSB Adjust In.
VOS Adjust In.
–5V Analog Power.
+5V Analog Power.
Digital Ground.
Digital Ground.
+5V Digital Power.
Conversion Clock In.
Conversion Clock Out. Can drive multiple
DSP101/DSP102s to synchronize conversion.
Select Synch Format In. If HIGH, SYNC will be
active High. If LOW, SYNC will be active Low.
See timing diagram (Figure 1).
Oscillator Point 1 Input/External Clock In. If using
external clock, drive with 74HC logic levels.
Connect to DGND if not used.
Oscillator Point 2 Output. Provides drive for
crystal oscillator. Make no electrical connection if
using external clock.
Data Synchronization Out. Active High when SSF
is HIGH; active Low when SSF is LOW.
Data Transfer Clock In.
No Internal Connection.
User Tag In. Data clocked into this pin is
appended to the conversion results on SOUT.
See timing diagram (Figure 1).
No Internal Connection.
Serial Data Out. MSB first, Binary Two’s
Complement format.
Convert Command In. Falling edge puts converter
into hold state, initiates conversion, and transmits
previous conversion results to DSP IC with
appropriate SYNC pulse.
Digital Ground.
No Internal Connection.
No Internal Connection.
No Internal Connection.
Bypass Capacitor. 10µF Tantalum to AGND.
Voltage on this pin is approximately 2.7V.
Reference Bypass. 0.1µF Ceramic to AGND.
Voltage on this pin is approximately 3.8V.
Analog Ground.
®
5
DSP101/102