DSP101 Datasheet, PDF (19/22 Pages) Burr-Brown (TI) – DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS

USING TMS320C31 TO GENERATE
ALL CONTROL SIGNALS
Figure 17 shows a circuit for using the TMS320C31 with a
DSP102 and a Burr-Brown DSP202 D/A to provide a two
channel analog I/O system. The flexibility of the TMS320C31
allows it to generate the data transfer clock (XCLK) and the
Convert Command, minimizing additional circuitry and syn-
chronizing the timing signals to the processor’s master
clock. In this circuit, the DSP102 and DSP202 are used in
their Cascade modes, transmitting and receiving two chan-
nels of data in a single 32-bit word. (See the Cascade Mode
section above.)
Table II shows how to set up the circuit in Figure 17 for a
44.1kHz conversion rate for both channels of the DSP102
A/D and both channels of the DSP202 D/A. Both inputs and
outputs will be simultaneously converted.
±2.75V Analog Input
DSP101
2 _VIN
16
XCLK
15
SYNC
20
SOUT
TTL Bit
Clock
TMS320C25
XCLK
FSX
TXD
12
SSF
+5V
21
CONV
Conversion Rate
Generator
NOTES: (1) TMS320C25 FSR external, 16-bit data.
FIGURE 16. Using DSP101 with TMS320C25.
DSP102
±2.75V Analog Input
Channel A
VINA
XCLK
SOUTA
SOUTB
±2.75V Analog Input
Channel B
1MΩ
VINB SYNC
OSC2
OSC1
SSF
CASC
CONV
12.288MHz
10pF
10pF
TMS3200C31
CLKR0
DR0
NC
CLKX0
DX0
FSR0
FSX0
TCLK0
+5V
+5V
+5V
+5V
+5V
FIGURE 17. Two Channel Analog I/O Using TMS320C31.
SERIAL PORT
Port Global Control Register
FSX/DX/CLKX Port Control Register
FSR/DR/CLKR Port Control Register
Receive/Transmit Timer Control Register
0x0EBC040
0x00000111
0x00000111
0x0000000F
TIMER
Timer Global Control Register
Timer Period Register
0x000002C1
0x000000B5
NOTE: Assumes TMS320C31 has 32MHz Master Clock.
TABLE II. TMS320C31 Register Settings for 44.1kHz Con-
version Rate in Figure 17.
19
DSP202
XCLK VOUTA
SINA
SINB
SYNC VOUTB
SSF
SWL
CASC
CONV
±3V Analog Output
Channel A
±3V Analog Output
Channel B
®
DSP101/102