CS4225 Datasheet, PDF (5/30 Pages) Cirrus Logic – Digital Audio Conversion System

CS4225
SWITCHING CHARACTERISTICS (TA = 25°C; VA+, VD+ = +5V, outputs loaded with 30pF)
Parameter
Symbol Min
Typ
Max Units
SCLK period
tsckw
80
-
-
ns
SCLK high time
tsckh
25
-
-
ns
SCLK low time
tsckl
25
-
-
ns
Input Transition Time
10% to 90% points
-
-
10
ns
Input Clock Frequency
Crystals
XTI
32
-
26000 kHz
32
-
26000 kHz
Input Clock (XTI) low time
30
-
-
ns
Input Clock (XTI) high time
30
-
-
ns
Input clock jitter tolerance
-
500
-
ps
PLL clock recovery frequency
LRCK, LRCKAUX
SCLK, SCLKAUX
32
-
50
kHz
2.048
-
3.200 MHz
CLKOUT duty cycle
45
50
55
%
Audio ADC’s & DAC’s sample rate
Fs
4
-
50
kHz
RST-PDN low time
(Note 5)
500
-
-
ns
MSB output from LRCK edge (Format 1 and 3)
tlrpd
-
-
50
ns
SDOUT output from SCLK edge
SDIN setup time before SCLK edge
tdpd
-
tds
-
-
50
ns
-
35
ns
SDIN hold time after SCLK edge
LRCK to SCLK delay (slave mode)
tdh
-
-
35
ns
tlrckd
35
-
-
ns
LRCK to SCLK setup (slave mode)
LRCK to SCLK alignment (master mode)
tlrcks
35
-
tmslr
-20
-
-
ns
20
ns
Note: 5. After Powering up the CS4225, RST-PDN should be held low for 50 ms to allow the voltage
reference to settle.
LRCK
LRCKAUX
(input)
t _lrckd
t _lrcks
t _sckh
t _sckl
SCLK*
SCLKAUX*
(output)
LRCK
LRCKAUX
(output)
SCLK*
SCLKAUX*
(input)
t _sckw
tmslr
SDIN1
SDIN2
DATAUX
tlrpd _tds
t _dh
t _dpd
SDOUT1
SDOUT2
MSB
MSB-1
Audio Ports Master Mode Timing
DS86PP8
*Active edge of SCLK, SCLKAUX depends on selected format.
Audio Ports Slave Mode and Data I/O timing
5