PCM3060 Datasheet, PDF (41/45 Pages) Burr-Brown (TI) – 24-BIT, 96/192-kHz ASYNCHRONOUS STEREO AUDIO CODEC

PCM3060
www.ti.com
DESIGN AND LAYOUT CONSIDERATIONS IN APPLICTION
SLAS533 – MARCH 2007
Power Supply Pins (V_CC, V_DD)
The digital and analog power supply lines to the PCM3060 should be bypassed to the corresponding ground
pins with 0.1-µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize the
dynamic performance of the ADC and DAC.
Although the PCM3060 has two power lines to maximize the potential of dynamic performance, using one
common source, 5-V power supply for V_CC and a 3.3-V power supply for V_DD which is generated from the 5-V
power supply for V_CC, is recommended to avoid unexpected problems, such as latch-up, from incorrect power
supply sequencing.
Grounding (AGND1, AGND2, SGND, DGND)
To maximize the dynamic performance of the PCM3060, the analog and digital grounds are not connected
internally. These points should have very low impedance to avoid digital noise and signal components feeding
back into the analog ground. So, they should be connected directly to each other under the parts to reduce the
potential of noise problems.
V_INL, V_INR Pins
A 4.7-µF electrolytic capacitor is recommended as the ac coupling capacitor, which gives a 3-Hz cutoff
frequency. If higher full-scale input voltage is required, it can be adjusted by adding only one series resistor to
the V_INX pins, although a small gain error is added due to variations of absolute input resistance of the
PCM3060. For example, adding 9.1 kΩ gives 2 Vrms full-scale with about 10% gain error.
V_COM Pin
Ceramic 0.1-µF and electrolytic 10-µF capacitors are recommended between V_COM and AGND to ensure low
source impedance of the ADC and DAC references. These capacitors should be located as close as possible to
the V_COM pins to reduce dynamic errors on ADC and DAC references.
V_OUTL+, V_OUTL–, V_OUTR+, V_OUTR– Pins
The differential to single-ended buffer with post LPF can be directly (without capacitor) connected to these
output pins, thereby minimizing the use of coupling capacitors for the 2-Vrms outputs. The output pins in
single-ended mode are assigned to V_OUTL+ and V_OUTR+ ; in single-ended mode, the V_OUTL– and V_OUTR– pins
must be open.
MODE Pin
This pin is a logic input with quad-state input capability.
The pin is connected to V_DD for High, to DGND for Low, and pulled up or pulled down through an external
resistor and for the two mid-states in order to distinguish the four input states. The pullup or pulldown resistor
must be 220 kΩ, ±5% tolerance.
System Clocks
The quality of SCKI1/2 may influence dynamic performance, as the PCM3060 (both ADC and DAC) operates
based on SCKI1/2. Therefore, it may be required to consider the jitter, duty, rise and fall time, etc. of the system
clocks.
The PCM3060 supports asynchronous operation between the ADC and DAC. Therefore, there is no restriction
on the relationship between SCKI1 and SCKI2 for digital operation, but it is strongly recommended to use a
common clock if the application does not require different base clock frequencies, like 44.1 kHz and 48 kHz.
Submit Documentation Feedback
41