CS42406 Datasheet, PDF (35/50 Pages) Cirrus Logic – 24-BIT, 192kHz 2-IN 6-OUT AUDIO CODEC

CS42406
4.6 Recommended Power-up Sequence
4.6.1 Stand Alone Mode
1) Hold DAC_RST and ADC_PDN low until the power supplies and configuration pins are stable, and the
master and left/right clocks are locked to the appropriate frequencies. In this state, the control port is
reset to its default settings.
2) Bring DAC_RST and ADC_PDN high. The CS42406 DAC will remain in a low power state with
DAC_VQ low and will initiate the Stand Alone power-up sequence after approximately 512
DAC_LRCK cycles in Single-Speed Mode (1024 DAC_LRCK cycles in Double-Speed Mode, and
2048 DAC_LRCK cycles in Quad-Speed Mode). The CS42406 ADC will begin the power-up se-
quence immediately following ADC_PDN going high.
4.6.2 Control Port Mode
1) Hold DAC_RST and ADC_PDN low until the power supplies are stable, and the master and left/right
clocks are locked to the appropriate frequencies. In this state, the control port is reset to its default
settings.
2) Bring DAC_RST and ADC_PDN high. The CS42406 DAC will remain in a low power state with
DAC_VQ low.
3) Load the desired register settings while keeping the PDN bit set to 1.
4) Set the PDN bit to 0. This will initiate the power-up sequence for the DAC, which lasts approximately
50 µs when the POPG bit is set to 0. If the POPG bit is set to 1, see Section 4.7 for a complete de-
scription of power-up timing.
4.7 Popguard^® Transient Control
The CS42406 uses a technique to minimize the effects of output transients during power-up and power-
down. This technology, when used with external DC-blocking capacitors in series with the audio outputs,
minimizes the audio transients commonly produced by single-ended single-supply converters. It is acti-
vated inside the CS42406 when the DAC_RST pin or PDN bit is enabled/disabled and requires no other
external control, aside from choosing the appropriate DC-blocking capacitors.
4.7.1 Power-up
When the device is initially powered-up, the audio outputs, AOUTAx and AOUTBx, are clamped to GND.
Following a delay of approximately 1000 DAC_LRCK cycles, each output begins to ramp toward the qui-
escent voltage. Approximately 10,000 DAC_LRCK cycles later, the outputs reach DAC_VQ and audio
output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge
to the quiescent voltage, minimizing the power-up transient.
4.7.2 Power-down
To prevent transients at power-down, the CS42406 must first enter its power-down state. When this oc-
curs, audio output ceases and the internal output buffers are disconnected from AOUTAx and AOUTBx.
In their place, a soft-start current sink is substituted which allows the DC-blocking capacitors to slowly dis-
charge. Once this charge is dissipated, the power to the device may be turned off and the system is ready
for the next power-on.
4.7.3 Discharge Time
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge be-
fore turning on the power or exiting the power-down state. If full discharge does not occur, a transient will
occur when the audio outputs are initially clamped to GND. The time that the device must remain in the
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