CS42406 Datasheet, PDF (28/50 Pages) Cirrus Logic – 24-BIT, 192kHz 2-IN 6-OUT AUDIO CODEC

CS42406
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE (Continued)
Parameter
SPI Mode
CCLK Clock Frequency
DAC_RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
Symbol
(Note 22)
(Note 23)
(Note 24)
(Note 24)
f_sclk
t_srs
t_spi
t_csh
t_css
t_scl
t_sch
t_dsu
t_dh
t_r2
t_f2
Min
-
500
500
1.0
20
--------1---------
MCLK
--------1---------
MCLK
40
15
-
-
Max
Unit
6
MHz
-
ns
-
ns
-
µs
-
ns
-
ns
-
ns
-
ns
-
ns
100
ns
100
ns
Notes: 22. t_spi only needed before first falling edge of CS after DAC_RST rising edge. t_spi = 0 at all other times.
23. Data must be held for sufficient time to bridge the transition time of CCLK.
24. For f_sclk < 1 MHz.
DAC_RST
t _srs
CS
t _spi t _css
t _scl t _sch
t _csh
CCLK
t _r2
t _f2
CDIN
t _dsu t _dh
Figure 32. Control Port Timing - SPI Mode
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DS614PP5