CS4362A Datasheet, PDF (32/47 Pages) Cirrus Logic – 114 dB, 192 kHz 6-channel D/A Converter

5. REGISTER DESCRIPTION
Note: All registers are read/write in I²C mode and write only in SPI, unless otherwise noted.
CS4362A
5.1 Mode Control 1 (address 01h)
7
CPEN
0
6
FREEZE
0
5
MCLKDIV
0
4
Reserved
0
3
DAC3_DIS
0
2
DAC2_DIS
0
1
DAC1_DIS
0
0
PDN
1
5.1.1 Control Port Enable (CPEN)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode can be
accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the registers
and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user should
write this bit within 10 ms following the release of Reset.
5.1.2 Freeze Controls (Freeze)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until the
FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously, en-
able the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
5.1.3 Master Clock DIVIDE ENABLE (mclkdiv)
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other
internal circuitry.
5.1.4 DAC Pair Disable (DACx_DIS)
Default = 0
0 - Enabled
1 - Disabled
Function:
When enabled the respective DAC channel pairx (AOUTAx and AOUTBx) will remain in a reset state. It is
advised that changes to these bits be made while the power down bit is enabled to eliminate the possibility
of audible artifacts.
32
DS617PP1