CS4227 Datasheet, PDF (27/36 Pages) Cirrus Logic – Six Channel, 20-Bit Codec

CS4227
2.24 Auxiliary Port Mode Byte (15)
7
ACK1
6
ACK0
5
AMS1
4
AMS0
3
ASCK
2
ADF2
1
ADF1
ADF2-ADF0
Data format
0 - Right justified, 20-bit data
1 - Right justified, 18-bit data
2 - Right justified, 16-bit data
3 - Left justified, 20-bit
4 - I²S compatible, 20-bit
5 - Not used
6 - Not used
7 - Not used
ASCK
Sets the polarity of clocking data
0 - Data clocked in on rising edge
1 - Data clocked in on falling edge
AMS1-AMS0
Sets the mode of the port.
0 - Slave
1 - Master Burst - SCLKAUXs are gated 128 Fs clocks
2 - Master Non-Burst - SCLKAUXs are evenly distributed in LRCKAUX frame
3 - Not used - default to slave
ACK1-ACK0
Set number of bit clocks per Fs period.
0 - 128
1 - 48 - Master Burst or Slave mode only
2 - 32 - All input formats will default to 16 bits.
3 - 64
This register defaults to 00h.
0
ADF0
DS281PP2
27