CS4227 Datasheet, PDF (17/36 Pages) Cirrus Logic – Six Channel, 20-Bit Codec

CS4227
CS
CCLK
CHIP
ADDRESS
MAP
DATA
CDIN
0010000
R/W
MSB
LSB
byte 1 byte n
CHIP
ADDRESS
0010000 _R/W
CDOUT
MAP = Memory Address Pointer
MSB
LSB MSB
LSB
High Impedance
Figure 11. Control Port Timing, SPI Mode
ports the same 5 formats as the audio DSP port in
multi-data line mode. LRCKAUX is used to indi-
cate left and right data samples, and the start of a
new sample period. SCLKAUX and LRCKAUX
may be output from the CS4227, or they may be
generated from an external source, as set by the
AMS1/0 control bits in the Auxiliary Port Mode
Byte (#15).
2.6 Control Port Signals
The control port is used to load all the internal set-
tings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference prob-
lems, the control port pins should remain static if
no operation is required.
The control port has 2 modes: SPI and I²C^®, with
the CS4227 as a slave device. The SPI mode is se-
lected by setting the SPI/I2C pin low, and I²C^® is
selected by setting the SPI/I2C pin high. The state
of this pin is continuously monitored.
2.6.1 SPI Mode
In SPI mode, CS is the CS4227 chip select signal,
CCLK is the control port bit clock, (input into the
CS4227 from the microcontroller), CDIN is the in-
put data line from the microcontroller, CDOUT is
the output data line to the microcontroller, and the
chip address is 0010000. Data is clocked in on the
rising edge of CCLK and out on the falling edge.
Figure 11 shows the operation of the control port in
SPI mode. To write to a register, bring CS low. The
first 7 bits on CDIN form the chip address, and they
must be 0010000. The eighth bit is a read/write in-
dicator (R/W), which should be low to write. The
next 8 bits form the Memory Address Pointer
(MAP), which is set to the address of the register
that is to be updated. The next 8 bits are the data
which will be placed into register designated by the
MAP. During writes, the CDOUT output stays in
the high impedance state. It may be externally
pulled high or low with a 47 kΩ resistor.
The CS4227 has a MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is a zero, then the MAP will stay constant for
successive reads or writes. If INCR is set to a 1,
then MAP will auto increment after each byte is
read or written, allowing block reads or writes of
successive registers.
To read a register, the MAP has to be set to the cor-
rect address by executing a partial write cycle
which finishes (CS high) immediately after the
MAP byte. The auto MAP increment bit (INCR)
may be set or not, as desired. To begin a read, bring
CS low, send out the chip address and set the
read/write bit (R/W) high. The next falling edge of
CCLK will clock out the MSB of the addressed
register (CDOUT will leave the high impedance
state). If the MAP auto increment bit is set to 1, the
data for successive registers will appear consecu-
tively.
DS281PP2
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