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| DSD1794 Datasheet, PDF (22/47 Pages) Texas Instruments – 24-BIT, 192-kHz SAMPLING, ADVANCED SEGMENT, AUDIO STRRO DIGITAL-TO-ALALOG CONVERTER | |||
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DSD1794
SLES077A â MARCH 2003 â REVISED NOVEMBER 2003
TIMING DIAGRAM
Start
t(BUF)
t(D-SU)
SDA
Repeated Start
t(D-HD)
www.ti.com
t(SDA-R)
t(SDA-F)
t(P-SU)
Stop
SCL
t(LOW)
t(SCL-R)
t(RS-HD)
t(SP)
t(S-HD)
t(HI)
t(SCL-F)
TIMING CHARACTERISTICS
PARAMETER
f(SCL) SCL clock frequency
t(RS-SU)
t(BUF) Bus free time between stop and start conditions
t(LOW) Low period of the SCL clock
t(HI)
High period of the SCL clock
t(RS-SU) Setup time for (repeated) start condition
t(S-HD) Hold time for (repeated) start condition
t(RS-HD)
t(D-SU) Data setup time
t(D-HD) Data hold time
t(SCL-R) Rise time of SCL signal
t(SCL-R1)
Rise time of SCL signal after a repeated start condition and after an
acknowledge bit
t(SCL-F) Fall time of SCL signal
t(SDA-R) Rise time of SDA signal
t(SDA-F) Fall time of SDA signal
t(P-SU)
C(B)
t(SP)
VNH
Setup time for stop condition
Capacitive load for SDA and SCL line
Pulse duration of suppressed spike
Noise margin at high level for each connected device (including hysteresis)
CONDITIONS
Standard
Fast
Standard
Fast
Standard
Fast
Standard
Fast
Standard
Fast
Standard
Fast
Standard
Fast
Standard
Fast
Standard
Fast
Standard
Fast
Standard
Fast
Standard
Fast
Standard
Fast
Standard
Fast
Fast
Standard
Fast
MIN
4.7
1.3
4.7
1.3
4
600
4.7
600
4
600
250
100
0
0
20 + 0.1 CB
20 + 0.1 CB
20 + 0.1 CB
20 + 0.1 CB
20 + 0.1 CB
20 + 0.1 CB
20 + 0.1 CB
20 + 0.1 CB
20 + 0.1 CB
20 + 0.1 CB
4
600
0.2 VDD
MAX
100
400
900
900
1000
300
1000
300
1000
300
1000
300
1000
300
400
50
UNIT
kHz
µs
µs
µs
ns
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
pF
ns
V
22
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