OPA3682 Datasheet, PDF (19/19 Pages) Burr-Brown (TI) – Triple, Wideband, Fixed Gain BUFFER AMPLIFIER With Disable

BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency
amplifier like the OPA3682 requires careful attention to
board layout parasitics and external component types. Rec-
ommendations that will optimize performance include:
tion vs Load plots. With a characteristic board trace imped-
ance defined based on board material and trace dimensions,
a matching series resistor into the trace from the output of
the OPA3682 is used as well as a terminating shunt resistor
at the input of the destination device. Remember also that the
terminating impedance will be the parallel combination of
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output pin can cause instability: on the non-inverting input,
it can react with the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all of the
ground and power planes around those pins. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.
b) Minimize the distance (< 0.25") from the power sup-
ply pins to high frequency 0.1µF decoupling capacitors.
At the device pins, the ground and power plane layout
should not be in close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize inductance
between the pins and the decoupling capacitors. The power
supply connections (on pins 4 and 7) should always be
decoupled with these capacitors. An optional supply
decoupling capacitor across the two power supplies (for
bipolar operation) will improve 2nd harmonic distortion
performance. Larger (2.2µF to 6.8µF) decoupling capacitors,
effective at lower frequency, should also be used on the main
supply pins. These may be placed somewhat farther from the
the shunt resistor and the input impedance of the destination
device: this total effective impedance should be set to match
the trace impedance. The high output voltage and current
capability of the OPA3682 allows multiple destination de-
vices to be handled as separate transmission lines, each with
their own series and shunt terminations. If the 6dB attenua-
tion of a doubly-terminated transmission line is unaccept-
able, a long trace can be series-terminated at the source end
only. Treat the trace as a capacitive load in this case and set
the series resistor value as shown in the plot of R_S vs
Capacitive Load. This will not preserve signal integrity as
well as a doubly-terminated line. If the input impedance of
the destination device is low, there will be some signal
attenuation due to the voltage divider formed by the series
output into the terminating impedance.
e) Socketing a high speed part like the OPA3682 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an ex-
tremely troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering the OPA3682
onto the board.
device and may be shared among several devices in the same
area of the PC board.
INPUT AND ESD PROTECTION
c) Careful selection and placement of external compo-
nents will preserve the high frequency performance of
the OPA3682. Resistors should be a very low reactance
type. Surface-mount resistors work best and allow a tighter
overall layout. Metal-film and carbon composition, axially-
leaded resistors can also provide good high frequency per-
formance. Again, keep their leads and PC board trace length
as short as possible. Never use wirewound type resistors in
a high frequency application. Other network components,
such as non-inverting input termination resistors, should also
be placed close to the package.
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-
board transmission lines. For short connections, consider
the trace and the input to the next device as a lumped
capacitive load. Relatively wide traces (50mils to 100mils)
The OPA3682 is built using a very high-speed complemen-
tary bipolar process. The internal junction breakdown volt-
ages are relatively low for these very small geometry de-
vices. These breakdowns are reflected in the Absolute Maxi-
mum Ratings table. All device pins have limited ESD protec-
tion using internal diodes to the power supplies as shown in
Figure 9.
These diodes provide moderate protection to input overdrive
voltages above the supplies as well. The protection diodes
can typically support 30mA continuous current. Where higher
currents are possible (e.g., in systems with ±15V supply
parts driving into the OPA3682), current-limiting series
resistors should be added into the two inputs. Keep these
resistor values as low as possible since high values degrade
both noise performance and frequency response.
should be used, preferably with ground and power planes
opened up around them. Estimate the total capacitive load
and set R_S from the plot of recommended R_S vs Capacitive
+V_CC
Load. Low parasitic capacitive loads (< 5pF) may not need
an R_S since the OPA3682 is nominally compensated to
operate with a 2pF parasitic load. If a long trace is required,
and the 6dB signal loss intrinsic to a doubly-terminated
External
Pin
Internal
Circuitry
transmission line is acceptable, implement a matched im-
pedance transmission line using microstrip or stripline tech-
–V _CC
niques (consult an ECL design handbook for microstrip and
stripline layout techniques). A 50Ω environment is normally
not necessary on board, and in fact, a higher impedance
FIGURE 9. Internal ESD Protection.
environment will improve distortion as shown in the Distor-
®
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OPA3682