CS5541 Datasheet, PDF (19/26 Pages) Cirrus Logic – Low-power, High-Voltage, 24-Bit Delta-Sigma ADC

CS5541
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Figure 14. Filter 1 Response (MCLK = 32.768 kHz)
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Figure 15. Filter 2 Response (MCLK = 32.768 kHz)
To accommodate higher throughput requirements,
each filter has a mode (53.7 SPS or 260 SPS
throughput) that outputs every single convolution.
This allows users to see input signal trends at high-
er update rates.
Note:
The converter’s digital filter characteristics
linearly scale with MCLK.
2.10 Sleep and Standby Modes
The CS5541 accommodates three power consump-
tion modes: normal, sleep, and standby. The nor-
mal power consumption mode is entered by default
after a power-on-reset. In this mode, the CS5541
typically consumes 750 µW.
The Sleep Mode is entered whenever the sleep
command, 0xAX, is issued to the serial port. The
ADC immediately enters sleep after the command
is issued, reducing the consumed power to around
30 µW. During sleep, most of the analog portion of
the chip is powered down and filter convolutions
are halted. To exit sleep (i.e. to return to normal
power consumption mode), the user must transmit
a data mode command. Since the sleep mode dis-
ables the oscillator, approximately a 500 ms crystal
oscillator start-up delay period is required before
the ADC returns to the normal power consumption
mode. Note that if an external clock is used, the
ADC will return to normal power mode within 3
milliseconds.
The Standby Mode is entered by writing 0xBX to
the part. The Standby Mode performs the same
function as the Sleep Mode except that the oscilla-
tor is not powered down. This eliminates the crystal
oscillator start-up time, with a return to normal
power within 3 milliseconds. Again, to exit standby
(i.e. to return to normal power consumption mode),
the user must transmit a data mode command. The
power during Standby will be around 75 µW.
2.11 Power-Up Sequence and Initialization
Care must be taken to assure that no pins are ever
taken below the negative analog supply (VA-) po-
tential. The analog and digital supplies should be
applied simultaneously to assure that the power-on
reset circuit will automatically reset the ADC when
both supplies are at acceptable levels.
Commands should not be sent to the ADC until a
stable clock is present. If a 32.768 kHz crystal is
being used, it will take approximately 500 ms for
the oscillator to stabilize after power has been ap-
plied to the converter. If a CMOS compatible
source with no start-up delay is used, then the ADC
is immediately ready for a command.
After a valid reset, the ADC is placed into the com-
mand state where it waits for a valid command to
execute. Once a valid conversion command has
been received, conversions will begin and data can
be read using the serial port.
Note:
The CS5541 includes an on-chip power-on
reset circuit to automatically reset the ADC
shortly after power-up. When power to the
CS5541 is applied, the ADC is held in a reset
condition until the master clock has started
and a counter-timer elapses (i.e. the
counter-timer counts 490 MCLK cycles to
DS500PP1
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