OPA3875 Datasheet, PDF (16/22 Pages) Burr-Brown (TI) – Triple 2:1 High-Speed Video Multiplexer

OPA3875
SBOS341B – DECEMBER 2006 – REVISED DECEMBER 2006
THERMAL ANALYSIS
Heatsinking or forced airflow may be required under
extreme operating conditions. Maximum desired
junction temperature will set the maximum allowed
internal power dissipation as discussed in this
document. In no case should the maximum junction
temperature be allowed to exceed +150°C.
Operating junction temperature (T_J) is given by T_A +
P_D × θ_JA. The total internal power dissipation (P_D) is
the sum of quiescent power (P_DQ) and additional
power dissipated in the output stage (P_DL) to deliver
load power. Quiescent power is simply the specified
no-load supply current times the total supply voltage
across the part. P_DL depends on the required output
signal and load but, for a grounded resistive load, is
at a maximum when the output is fixed at a voltage
equal to 1/2 of either supply voltage (for equal
bipolar supplies). Under this condition P_DL = V_S2/(4 ×
R_L), where R_L includes feedback network loading.
Note that it is the power in the output stage and not
in the load that determines internal power
dissipation.
As a worst-case example, compute the maximum T_J
using an OPA3875 in the circuit of Figure 26
operating at the maximum specified ambient
temperature of +85°C with all three outputs driving a
grounded 100Ω load to +2.5V:
P_D = 10V ´ 36mA + 3(5²/4 ´ (100W || 804W)) = 571mW
Maximum T_J = +85°C + (0.57W ´ 85°C/W) = 133°C
This worst-case condition is approaching the
maximum +150°C junction temperature. Normally,
this extreme case is not encountered. Careful
attention to internal power dissipation is required.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high
frequency amplifier such as the OPA3875 requires
careful attention to board layout parasitics and
external component types. Recommendations that
will optimize performance include:
a) Minimize parasitic capacitance to any AC
ground for all of the signal I/O pins. Parasitic
capacitance on the output pin can cause instability:
on the noninverting input, it can react with the source
impedance to cause unintentional bandlimiting. To
reduce unwanted capacitance, a window around the
signal I/O pins should be opened in all of the ground
and power planes around those pins. Otherwise,
ground and power planes should be unbroken
elsewhere on the board.
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b) Minimize the distance (< 0.25") from the
power-supply pins to high frequency 0.1µF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance
between the pins and the decoupling capacitors. The
power-supply connections (on pins 9, 11, 13, and 15)
should always be decoupled with these capacitors.
An optional supply decoupling capacitor across the
two power supplies (for bipolar operation) will
improve 2nd-harmonic distortion performance. Larger
(2.2µF to 6.8µF) decoupling capacitors, effective at
lower frequency, should also be used on the main
supply pins. These may be placed somewhat farther
from the device and may be shared among several
devices in the same area of the PCB.
c) Careful selection and placement of external
components will preserve the high-frequency
performance of the OPA3875. Resistors should be
a very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout.
Metal-film and carbon composition, axially leaded
resistors can also provide good high-frequency
performance. Again, keep their leads and PCB trace
length as short as possible. Never use wirewound
type resistors in a high-frequency application. Other
network components, such as noninverting input
termination resistors, should also be placed close to
the package.
d) Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up
around them. Estimate the total capacitive load and
set R_S from the plot of Figure 5. Low parasitic
capacitive loads (< 5pF) may not need an R_S
because the OPA3875 is nominally compensated to
operate with a 2pF parasitic load. If a long trace is
required, and the 6dB signal loss intrinsic to a
doubly-terminated transmission line is acceptable,
implement a matched impedance transmission line
using microstrip or stripline techniques (consult an
ECL design handbook for microstrip and stripline
layout techniques). A 50Ω environment is normally
not necessary on board, and in fact, a higher
impedance environment will improve distortion as
shown in the Distortion versus Load plots.
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