SHC615 Datasheet, PDF (15/19 Pages) Burr-Brown (TI) – Wide-Bandwidth, DC RESTORATION CIRCUIT

V+
12
V_I
100Ω _{3 B}
C
OTA
G ≈1
V_OS ≈ 0
V_I
E
2
V_O
V_O
R_E
G ≈1
R_E
V_OS ≈ 0.7V
(b) Common-C Amplifier
(Buffer)
V–
(a) Common Collector Amplifier
(Emitter Follower)
G=
1
≈1
1+ ¹
g_m • R_E
R_O =
1
g_m
V+
R_L
V_O
G = – ^RL ≈ – ^RL
R_E +
1
g_m
R_E
Non-Inverting Gain
V_OS ≈ several volts
100Ω
R_E
3B
V_I
(a) Common-Base
Amplifier
12
C
OTA
E
2
R_E
V_O
Inverting Gain
R_L
V_OS ≈ 0
V_I
(b) Common-B Amplifier
FIGURE 3. a) Common Collector Amplifier Using a Discrete
Transistor; b) Common-C Amplifier Using the
OTA Portion of the SHC615.
SAMPLING COMPARATOR
The SHC615 sampling comparator features a very short
2.2ns propagation delay and utilizes a new switching circuit
architecture to achieve excellent speed and precision.
It provides high impedance inverting and non-inverting
inputs, a high-impedance current source output and a TTL-
CMOS-compatible Hold Control Input.
The sampling comparator consists of an operational transcon-
ductance amplifier (OTA), a buffer amplifier, and a subse-
quent switching circuit. The OTA and buffer amplifier are
directly tied together at the buffer outputs to provide the two
identical high-impedance inputs and high open-loop transcon-
ductance. Even a small differential input voltage multiplied
with the high transconductance results in an output cur-
rent—positive or negative—depending upon the input polar-
ity. This is similar to the low or high status of a conventional
comparator. The current source output features high output
impedance, output bias compensation, and is optimized for
charging a capacitor in DC restoration, nanosecond integra-
tors, peak detectors and S/H circuits. The typical comparator
output current is ±3.2mA and the output bias current is
minimized to typically ±10µA in the sampling mode.
This innovative circuit achieves the slew rate representatives
of an open-loop design. In addition, the acquisition slew
current for a hold or storage capacitor is higher than standard
diode bridge and switch configurations, removing a main
contributor to the limits of maximum sampling rate and
input frequency.
The switching circuits in the SHC615 use current steering
(versus voltage switching) to provide improved isolation
between the switch and analog sections. This results in low
aperture time sensitivity to the analog input signal, reduced
power supply and analog switching noise. Sample-to-hold
peak switching is 40fC.
FIGURE 4. a) Common Base Amplifier Using a Discrete
Transistor; b) Common-B Amplifier Using the
OTA Portion of the SHC615.
The additional offset voltage or switching transient induced
on a capacitor at the current source output by the switching
charge can be determined by the following formula:
Offset(V) = ^Charge(pC)
C_H Total(pF)
The switching stage input is insensitive to the low slew rate
performance of the hold control command and compatible
with TTL/CMOS logic levels. With a TTL logic high, the
comparator is active, comparing the two input voltages and
varying the output current accordingly. With a TTL logic
low, the comparator output is switched off.
APPLICATION INFORMATION
The SHC615 operates from ±5V power supplies (±6V maxi-
mum). Do not attempt to operate with larger power supply
voltages or permanent damage may occur.
Inputs of the SHC615 are protected with internal diode
clamps as shown in Figure 1. These protection diodes can
safely conduct 10mA continuously (30mA peak). If input
voltages can exceed the power supply voltages by 0.7V, the
input signal current must be limited.
BASIC CONNECTIONS
Figure 6 shows the basic connections required for operation.
These connections are not shown in subsequent circuit
diagrams. Power supply bypass capacitors should be located
as close as possible to the device pins. Solid tantalum
capacitors are generally best. See “Circuit Layout” at the end
of the applications discussion for further suggestions on
layout.
®
15
SHC615