DAC8501 Datasheet, PDF (12/18 Pages) Burr-Brown (TI) – Low-Power, Rail-to-Rail Output, 16-Bit Serial Input DIGITAL-TO-ANALOG CONVERTER

OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output which gives an output range of
0V to V_DD; it is capable of driving a load of 2kΩ in parallel with
1000pF to GND. The source and sink capabilities of the
output amplifier can be seen in the typical characteristics.
The slew rate is 1V/µs with a full-scale settling time of 8µs
with the output unloaded.
The inverting input of the output amplifier is brought out to the
V_FB pin which allows for better accuracy in critical applica-
tions by tying the V_FB point and the amplifier output together
directly at the load. Other signal conditioning circuitry may
also be connected between these points for specific applica-
tions.
MULTIPLYING MODE OPTIMIZATIONS
The DAC8501 is a version of the DAC8531 optimized for
multiplying mode at a typical bandwidth of up to 350kHz,
which gives better phase and gain performance.
Two aspects of the DAC8501 operation are affected by the
optimizations. The resistor string in the DAC8531 is discon-
nected from the reference input when power-down mode is
entered, but in the DAC8501, the resistor string continues to
draw current from the reference input during power-down
mode.
The DAC8501 has slightly different offset characteristics
from the DAC8531: the DAC8501 may output 0V for the first
few hundred codes, whereas the DAC8531 typically has far
fewer such dead codes near 0. Offset and gain errors are
measured from code 0200_H for both devices, so specifica-
tions are not affected. In all other respects, the DAC8531 and
DAC8501 operate identically.
Multiplying-mode bandwidth is measured at both small-signal
and full-power levels. Bandwidth at full-power amplitude,
which is typically 64kHz, is limited by the 1V/µs slew rate of
the output amplifier. Small-amplitude signals that do not
cause the amplifier to slew are bandlimited by the output
amplifier to approximately 350kHz. If the design approaches
either of these limits, the DAC8501 must be tested in the
application to ensure that it meets the needed requirements.
SERIAL INTERFACE
The DAC8501 has a 3-wire serial interface (SYNC, SCLK, and
D_IN), which is compatible with SPI, QSPI, and Microwire interface
standards as well as most DSPs, (see the Serial Write Operation
timing diagram for an example of a typical write sequence).
The write sequence begins by bringing the SYNC line LOW, data
from the D_IN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30MHz, making the DAC8501 compatible with high-speed
DSPs. On the 24th falling edge of the serial clock, the last data
bit is clocked in and the programmed function is executed (i.e., a
change in DAC register contents and/or a change in the mode of
operation).
At this point, the SYNC line can be kept LOW or brought HIGH.
In either case, it must be brought HIGH for a minimum of 33ns
before the next write sequence so that a falling edge of SYNC
can initiate the next write sequence. As the SYNC buffer draws
more current when the SYNC signal is HIGH than it does when
it is LOW, SYNC must be idled LOW between write sequences
for lowest power operation of the part; as mentioned above, it
must be brought HIGH again just before the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide, as shown in
Figure 3. The first six bits are don’t cares. The next two bits (PD1
and PD0) are control bits that control which mode of operation the
part is in (normal mode or any one of three power-down modes):
there is a more complete description of the various modes in the
Power-Down Modes section. The next 16 bits are the data bits
which are transferred to the DAC register on the 24th falling edge
of SCLK.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept LOW for at
least 24 falling edges of SCLK and the DAC is updated on the
24th falling edge. However, if SYNC is brought HIGH before the
24th falling edge, this acts as an interrupt to the write sequence.
When this happens, the shift register is reset and the write
sequence is seen as invalid. Neither an update of the DAC
register contents or a change in the operating mode occurs, as
shown in Figure 4.
DB23
DB0
X X X X X X PD1 PD0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
FIGURE 3. Data Input Register.
CLK
SYNC
24th Falling Edge
D_IN
DB23
DB0
Invalid Write Sequence:
SYNC HIGH before 24th Falling Edge
FIGURE 4. SYNC Interrupt Facility.
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24th Falling Edge
DB23
DB0
Valid Write Sequence: Output Updates
on the 24th Falling Edge
DAC8501
SBAS212A