CS22250 Datasheet, PDF (12/32 Pages) Cirrus Logic – WIRELESS 10BT CONTROLLER

SMA7
SMA8
SMA9
SMA10
SMA11
SMD[7:0]
SMD[15:8]
Output
Address bit7. Also shared as boot-rom address bit7. Also used
during reset to latch in the strap value for freq_sel(1). Freq_sel(2:0) is
used to select the multiplication factor for the internal PLL (000=1x and
111=8x).
Output
Address bit8. Also shared as boot-rom address bit8. Also used during
reset to latch in the strap value for freq_sel(2). Freq_sel(2:0) is used to
select the multiplication factor for the internal PLL (000=1x and 111=8x).
Output
Address bit9. Also shared as boot-rom address bit9. Also used during
reset to latch in the strap value for sdram_delay(0). Sdram_delay(2:0) is
used to select the delay factor for the internal memory clock (000=0ns
and 111=1.75ns with each .25ns increments).
Output
Address bit10. Also shared as boot-rom address bit10. Also used during
reset to latch in the strap value for sdram_delay(1). Sdram_delay(2:0) is
used to select the delay factor for the internal memory clock (000=0ns
and 111=1.75ns with each .25ns increments).
Output
Address bit11. Also shared as boot-rom address bit11. Also used during
reset to latch in the strap value for sdram_delay(2). Sdram_delay(2:0) is
used to select the delay factor for the internal memory clock (000=0ns
and 111=1.75ns with each .25ns increments).
Bidirectional
Data bus. The data bus contains the data to be written to memory on a
write cycle and the read return data on a read cycle.
Bidirectional
Shared data bus. The data bus contains the data to be written to RAM
memory on a write cycle and the read return data on a read cycle. Data
bit [15:8] is also shared as boot ROM address bit [19:12].
CS22250 Wireless 10BT Controller
12 of 32
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DS551PP2 Rev. 3.0