ADS7813 Datasheet, PDF (11/17 Pages) Burr-Brown (TI) – Low-Power, Serial 16-Bit Sampling ANALOG-TO-DIGITAL CONVERTER

might be possible to use the rising edge of the DATACLK
signal. However, one extra clock period (not shown in
Figures 6, 7, and 8) is needed for the final bit.
The external DATACLK signal must be LOW or CS must
be HIGH prior to BUSY rising (see time t₂₅ in Figures 7 and
8). If this is not observed during this time, the output shift
register of the ADS7813 will not be updated with the
conversion result. Instead, the previous contents of the shift
register will remain and the new result will be lost.
Before reading the next three paragraphs, consult the Sensi-
tivity to External Digital Signals section of this data sheet.
This will explain many of the concerns regarding how and
when to apply the external DATACLK signal.
External DATACLK Active After the Conversion
The preferred method of obtaining the conversion result is to
provide the DATACLK signal after the conversion has been
completed and before the next conversion starts—as shown
in Figure 6. Note that the DATACLK signal should be static
before the start of the next conversion. If this is not ob-
served, the DATACLK signal could affect the voltage that
is acquired.
External DATACLK Active During the Next Conversion
Another method of obtaining the conversion result is shown
in Figure 7. Since the output shift register is not updated
until the end of the conversion, the previous result remains
valid during the next conversion. If a fast clock (≥ 2MHz)
can be provided to the ADS7813, the result can be read
during time t₂. During this time, the noise from the
DATACLK signal is less likely to affect the conversion
result.
CONV
t₁
t₂
BUSY
t₂₁
t₂₄
t₂₃
t₂₅
DATACLK
1
2
3
4
15
16
DATA
t₁₉
t₂₂
t₂₀
MSB
Bit 14 Bit 13
Bit 1
LSB
1
MSB
FIGURE 7. Serial Data Timing, External Clock, Clocking During the Next Conversion (EXT/INT HIGH,
CS LOW).
CONV
BUSY
t₅
t₄
t₂₄
t₂₅
DATACLK
1
2
n
n+1
15
16
DATA
MSB
Bit 14
Bit n
Bit n-1 Bit 1
LSB
FIGURE 8. Serial Data Timing, External Clock, Clocking After the Conversion Completes and During the Next Conversion
(EXT/INT HIGH, CS LOW).
®
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ADS7813