ADS809 Datasheet, PDF (1/20 Pages) Burr-Brown (TI) – 12-Bit, 80MHz Sampling ANALOG-TO-DIGITAL CONVERTER

ADS809
ADS809
SBAS170C – NOVEMBER 2000 – REVISED JANUARY 2003
12-Bit, 80MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q DYNAMIC RANGE:
SNR: 65dB at 10MHz f_IN
SFDR: 68dB at 10MHz f
IN
q PREMIUM TRACK-AND-HOLD:
Low Jitter: 0.5ps rms
Differential or Single-Ended Inputs
Selectable Full-Scale Input Range
q FLEXIBLE CLOCKING:
Differential or Single-Ended
Accepts Sine or Square Wave Clocking
Down to 0.5Vp-p
Variable Threshold Level
APPLICATIONS
q BASESTATION WIDEBAND RADIOS:
CDMA, GSM, TDMA, 3G, AMPS, and NMT
q TEST INSTRUMENTATION
q CCD IMAGING
+V_S
ADS809
DESCRIPTION
The ADS809 is a high-dynamic range, 12-bit, 80MHz, pipelined
Analog-to-Digital Converter (ADC). It includes a high-band-
width linear track-and-hold that has a low jitter of only 0.5ps
rms, leading to excellent Signal-to-Noise Ratio (SNR) perfor-
mance. The clock input can accept a low-level differential sine
wave or square wave signal down to 0.5Vp-p, further improv-
ing the SNR performance. It also accepts a single-ended
clock signal and has flexible threshold levels.
The ADS809 has a 2Vp-p differential input range (1Vp-p • 2
inputs) for optimum signal-to-noise ratio. The differential
operation gives the lowest even-order harmonic compo-
nents. A lower input voltage of 1.5Vp-p or 1Vp-p can also be
selected using the internal references, further optimizing
Spurious-Free Dynamic Range (SFDR). Alternatively, a single-
ended input range can be used by tying the IN input to the
common-mode voltage if desired.
The ADS809 also provides an over-range flag that indicates
when the input signal has exceeded the converter’s full-scale
range. This flag can also be used to reduce the gain of the
front-end signal conditioning circuitry. It also employs digital
error-correction techniques to provide excellent differential
linearity for demanding imaging applications. The ADS809 is
available in a small TQFP-48 PowerPAD™ thermally-
enhanced package.
PowerPAD is a registered trademark of Texas Instruments.
DV
CLK
Timing Circuitry
CLK
1Vp-p
IN
1Vp-p
IN
T&H
12-Bit
Pipelined
ADC Core
Error
Correction
Logic
D0
3-State
Outputs
•••
D11
CM
(+2.5V)
Reference Ladder
and Driver
Reference and
Mode Select
OVR
REFT
V_REF SEL1 SEL2 REFB
OE VDRV
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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