BS616LV8025 Datasheet, PDF (6/11 Pages) Brilliance Semiconductor – Very Low Power/Voltage CMOS SRAM 512K x 16 or 1M x 8 bit switchable

BSI
„ AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
„ AC TEST LOADS AND WAVEFORMS
5.0V
OUTPUT
1928 Ω
5.0V
OUTPUT
1928 Ω
INCLUDING
JIG AND
SCOPE
100PF
1020 Ω
INCLUDING
JIG AND
SCOPE
5PF
1020 Ω
FIGURE 1A
OUTPUT
THEVENIN EQUIVALENT
667 Ω
FIGURE 1B
1.73V
Vcc
GND
ALL INPUT PULSES
10%
→
90% 90%
←
→
FIGURE 2
10%
← 5ns
BS616LV8025
„ KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
„ AC ELECTRICAL CHARACTERISTICS ( TA = 0^oC to +70^oC, Vcc=5V )
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
E1LQV
t
E2LQV
t
BA
t
GLQV
t
ELQX
t
BE
t
GLQX
t
EHQZ
t
BDO
t
GHQZ
t
AXQX
PARAMETER
NAME
t
RC
t
AA
t
ACS1
t
ACS2
t (1)
BA
t
OE
t
CLZ
t
BE
t
OLZ
t
CHZ
t
BDO
t
OHZ
t
OH
DESCRIPTION
BS616LV8025-55
MIN. TYP. MAX.
Read Cycle Time
55
Address Access Time
55
Chip Select Access Time
(CE1)
55
Chip Select Access Time
(CE2)
55
Data Byte Control Access Time _(LB,UB)
30
Output Enable to Output Valid
30
Chip Select to Output Low Z
(CE2,CE1) 10
Data Byte Control to Output Low Z _{(LB,UB) 10}
Output Enable to Output in Low Z
10
Chip Deselect to Output in High Z (CE2,CE1) ₀
30
Data Byte Control to Output High Z _(LB,UB)
0
30
Output Disable to Output in High Z
0
25
Output Disable to Output Address Change
10
NOTE :
1. tBA is 30ns/35ns (@speed=55ns/70ns) with address toggle .
tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle .
BS616LV8025-70
MIN. TYP. MAX.
70
70
70
70
35
35
10
10
10
0
35
0
35
0
30
10
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R0201-BS616LV8025
6
Revision 2.4
April 2002