BS616LV8025 Datasheet, PDF (1/11 Pages) Brilliance Semiconductor – Very Low Power/Voltage CMOS SRAM 512K x 16 or 1M x 8 bit switchable

BSI ^{Very Low Power/Voltage CMOS SRAM}
512K x 16 or 1M x 8 bit switchable
BS616LV8025
„ FEATURES
• Very low operation voltage : 4.5 ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade: 45mA (Max.) operating current
I-grade : 50mA (Max.) operating current
3uA (Typ.) CMOS standby current
• High speed access time :
-55 55ns (Max.) at Vcc= 5.0V
-70 70ns (Max.) at Vcc= 5.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
„ DESCRIPTION
The BS616LV8025 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits or
1,048,576 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 3uA and maximum access time of 55/70ns in 5.0V operation.
Easy memory expansion is provided by an active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
The BS616LV8025 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV8025 is available in 48-pin BGA type.
„ PRODUCT FAMILY
PRODUCT OPERATING
Vcc
FAMILY TEMPERATURE RANGE
SPEED
(ns)
Vcc=5V
BS616LV8025BC +0^OC to +70^OC 4.5V ~ 5.5V 55/70
POWER DISSIPATION
STANDBY
Operating
(I CCSB1 , Max)
(ICC , Max)
Vcc=5V
Vcc=5V
30uA
45mA
PKG TYPE
BGA-48-0810
BS616LV8025BI -40^OC to +85^OC 4.5V ~5.5V 55/70
100uA
50mA
BGA-48-0810
„ PIN CONFIGURATIONS
„ BLOCK DIAGRAM
1
2
3
4
5
6
A LB OE A0 A1 A2 CE2
B D8 UB A3 A4 CE1 D0
C D9 D10 A5 A6 D1 D2
D VSS D11 A17 A7 D3 VCC
E VCC ^D12 VSS ^{A16 D4 VSS}
F D14 D13 A14 A15 ^{D5 D6}
G D15 CI.O A12 A13 WE D7
H A18 A8 A9 A10 A11 SAE.
48-Ball CSP top View
A15
A14
A13
A12
Address
A11
22
2048
A10
Input
Row
A9
Buffer
A8
A17
Decoder
A7
A6
D0
.
.
.
.
.
.
.
.
D15
16(8)
16(8)
Data
Input
Buffer
16(8)
16(8)
Data
Output
Buffer
Memory Array
2048 x 4096
4096
Column I/O
Write Driver
Sense Amp
256(512)
Column Decoder
CE1
CE2
WE
OE
UB
LB
CIO
Vdd
GND
Control
16(18)
Address Input Buffer
A16 A0 A1 A2 A3 A4 A5 A18 _(SAE)
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
R0201-BS616LV8025
1
Revision 2.4
April 2002