BS62LV8001_06 Datasheet, PDF (5/10 Pages) Brilliance Semiconductor – Very Low Power CMOS SRAM 1M X 8 bit

n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1 ^(1,2,4)
t_RC
ADDRESS
D_OUT
t_AA
t_OH
READ CYCLE 2 ^(1,3,4)
CE1
CE2
D_OUT
t_ACS1
t_ACS2
t_CLZ⁽⁵⁾
READ CYCLE 3 ^{(1, 4)}
ADDRESS
OE
CE1
CE2
D_OUT
t_RC
t_AA
t_OE
t_OLZ
t_CLZ1^(5)tACS1
t_ACS2
t_CLZ2⁽⁵⁾
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
R0201-BS62LV8001
5
BS62LV8001
t_OH
t_CHZ1, t_CHZ2⁽⁵⁾
t_OH
t_OHZ⁽⁵⁾
t_CHZ1^(1,5)
t_CHZ2^(1,5)
Revision 2.3
May.
2006