BS62LV8001_06 Datasheet, PDF (1/10 Pages) Brilliance Semiconductor – Very Low Power CMOS SRAM 1M X 8 bit

Very Low Power CMOS SRAM
1M X 8 bit
Pb-Free and Green package materials are compliant to RoHS
BS62LV8001
n FEATURES
Ÿ Wide VCC operation voltage : 2.4V ~ 5.5V
Ÿ Very low power consumption :
VCC = 3.0V Operation current : 31mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 0.8uA (Typ.) at 25 ^OC
VCC = 5.0V Operation current : 76mA (Max.) at 55ns
10mA (Max.) at 1MHz
Standby current : 3.5uA (Typ.) at 25^OC
Ÿ High speed access time :
-55
55ns (Max.) at VCC : 3.0~5.5V
-70
70ns (Max.) at VCC : 2.7~5.5V
Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE1, CE2 and OE options
Ÿ Three state outputs and TTL compatible
Ÿ Fully static operation
Ÿ Data retention supply voltage as low as 1.5V
n POWER CONSUMPTION
n DESCRIPTION
The BS62LV8001 is a high performance, very low power CMOS
Static Random Access Memory organized as 1,048,576 by 8 bits
and operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.8uA at 3.0V/25^OC and maximum access time of 55ns at
3.0V/85^OC.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2), and active LOW output
enable (OE) and three-state output drivers.
The BS62LV8001 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS62LV8001 is available in DICE form, JEDEC standard 44-pin
TSOP II and 48-ball BGA package.
PRODUCT
FAMILY
OPERATING
TEMPERATURE
STANDBY
(ICCSB1, Max)
VCC=5.0V VCC=3.0V
BS62LV8001DC
BS62LV8001EC
BS62LV8001FC
Commercial
+0^OC to +70^OC
25uA
4.0uA
BS62LV8001EI
BS62LV8001FI
Industrial
-40^OC to +85^OC
50uA
8.0uA
POWER DISSIPATION
1MHz
VCC=5.0V
10MHz
Operating
(ICC, Max)
fMax.
1MHz
9mA 39mA 75mA 1.5mA
10mA 40mA 76mA 2mA
VCC=3.0V
10MHz
19mA
20mA
fMax.
30mA
31mA
PKG TYPE
DICE
TSOP II-44
BGA-48-0912
TSOP II-44
BGA-48-0912
n PIN CONFIGURATIONS
A4 1
44 A5
A3 2
43 A6
A2 3
42 A7
A1 4
41 OE
A0 5
40 CE2
CE1 6
39 A8
NC 7
38 NC
NC 8
37 NC
DQ0 9
36 DQ7
DQ1 10
35 DQ6
VCC 11 BS62LV8001EC 34 VSS
VSS 12
DQ2 13
BS62LV8001EI
33 VCC
32 DQ5
DQ3 14
31 DQ4
NC 15
30 NC
NC 16
29 NC
WE 17
28 A9
A19 18
27 A10
A18 19
26 A11
A17 20
25 A12
A16 21
24 A13
A15 22
23 A14
1
2
3
4
5
6
A
NC OE
A0
A1
A2 CE2
B
NC NC
A3
A4 CE1 NC
C
DQ0 NC A5
A6
NC DQ4
D
VSS DQ1 A17 A7 DQ5 VCC
E
VCC DQ2 NC A16 DQ6 VSS
F
DQ3 NC A14 A15 NC DQ7
n BLOCK DIAGRAM
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE1
CE2
WE
OE
VCC
VSS
Address
22
Input
Buffer
Row
Decoder
2048
Memory Array
2048 x 4096
8
8
Control
Data
Input
8
Buffer
Data
8
Output
Buffer
4096
Column I/O
Write Driver
Sense Amp
512
Column Decoder
18
Address Input Buffer
A11 A9 A8 A3 A2 A1 A0 A10 A19
G
NC NC A12 A13 WE NC
H
A18 A8
A9 A10 A11 A19
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
R0201-BS62LV8001
1
Revision 2.3
May.
2006